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general description the max9257 serializer pairs with the max9258 deseri-alizer to form a complete digital video serial link. the max9257/max9258 feature programmable parallel data width, parallel clock frequency range, spread spectrum, and preemphasis. an integrated control channel trans- fers data bidirectionally at power-up during video blank- ing over the same differential pair used for video data. this feature eliminates the need for external can or lin interface for diagnostics or programming. the clock is recovered from input serial data at max9258, hence eliminating the need for an external reference clock. the max9257 serializes 10, 12, 14, 16, and 18 bits with the addition of two encoding bits for ac-coupling. the max9258 deserializer links with the max9257 to deseri- alize a maximum of 20 (data + encoding) bits per pixel/parallel clock period for a maximum serial-data rate of 840mbps. the word length can be adjusted to accommodate a higher pixel/parallel clock frequency. the pixel clock can vary from 5mhz to 70mhz, depend- ing on the serial-word length. enabling parity adds two parity bits to the serial word. the encoding bits reduce isi and allow ac-coupling. the max9258 receives programming instructions from the electronic control unit (ecu) during the control channel and transmits to the max9257 over the serial video link. the instructions can program or update the max9257, max9258, or an external peripheral device, such as a camera. the max9257 communicates with the peripheral device with i 2 c or uart. the max9257/max9258 operate from a +3.3v coresupply and feature separate supplies for interfacing to +1.8v to +3.3v logic levels. these devices are avail- able in 40-lead tqfn or 48-pin lqfp packages. these devices are specified over the -40? to +105? temper- ature range. applications automotive camerasindustrial cameras navigation systems display in-vehicle entertainment systems features ? 10/12/14/16/18-bit programmable parallel datawidth ? max9258 does not require reference clock ? parity protection for video and control channels ? programmable spread spectrum ? programmable rising or falling edge for hsync,vsync, and clock ? up to 10 remotely programmable gpio onmax9257 ? automatic resynchronization in case of loss oflock ? max9257 parallel clock jitter filter pll withbypass ? dc-balanced coding allows ac-coupling ? 5 levels of preemphasis for up to 20m stp cabledrive ? integrity test using on-chip programmableprbs generator and checker ? lvds i/o meet iso 10605 esd protection (?0kvcontact and ?0kv air discharge) ? lvds i/o meet iec 61000-4-2 esd protection(?kv contact and ?0kv air discharge) ? lvds i/o meet ?00v machine model esdprotection ? -40? to +105? operating temperature range ? space-saving, 40-pin tqfn (5mm x 5mm) withexposed pad or 48-pin lqfp packages ? +3.3v core supply max9257/max9258 fully programmable serializer/deserializer with uart/i 2 c control channel ________________________________________________________________ maxim integrated products 1 19-1044; rev 1; 3/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information part temp range pin-package max9257 gtl/v+ -40? to +105? 40 tqfn-ep* max9257gcm/v+ -40? to +105? 48 lqfp max9258 gcm/v+ -40? to +105? 48 lqfp /v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. typical operating circuit and pin configurations appear at end of data sheet. downloaded from: http:///
max9257/max9258 2 _______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc _ to gnd .........................................................-0.5v to +4.0v any ground to any ground...................................-0.5v to +0.5v sdi+, sdi-, sdo+, sdo- to gnd..........................-0.5v to +4.0v sdo+, sdo- short circuit to gnd or v cclvds .........continuous din[0:15], gpio[0:9], pclk_in, hsync_in, vsync_in, scl/tx, sda/rx, rem to gnd ............-0.5v to (v ccio + 0.5v) dout[0:15], pclk_out, hsync_out, vsync_out, rx, lock, tx, pd , error to gnd ........-0.5v to (v ccout + 0.5v) continuous power dissipation (t a = +70?) 40-lead tqfn multilayer pcb (derate 35.7mw/? above +70?) .....2857mw 48-lead lqfp multilayer pcb (derate 21.7mw/? above +70?) .....1739mw junction-to-case thermal resistance ( jc ) (note 1) 40-lead tqfn .............................................................1.7?/w 48-lead lqfp ...............................................................10?/w junction-to-ambient thermal resistance ( ja ) (note 1) 40-lead tqfn ..............................................................28?/w 48-lead lqfp ...............................................................46?/w esd protection human body model (r d = 1.5k , c s = 100pf) all pins to gnd ..............................................................?kv iec 61000-4-2 (r d = 330 , c s = 150pf) contact discharge (sdi+, sdi-, sdo+, sdo-) to gnd................................?kv air discharge (sdi+, sdi-, sdo+, sdo-) to gnd..............................?0kv iso 10605 (r d = 2k , c s = 330pf) contact discharge (sdi+, sdi-, sdo+, sdo-) to gnd..............................?0kv air discharge (sdi+, sdi-, sdo+, sdo-) to gnd..............................?0kv machine model (r d = 0 , c s = 200pf) all pins to gnd ............................................................?00v storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? max9257 dc electrical characteristics(v cc_ = +3.0v to +3.6v, r l = 50 ?%, t a = -40? to +105?, unless otherwise noted. typical values are at v cc_ = +3.3v, t a = +25?.) (notes 2, 3) parameter symbol conditions min typ max units single-ended inputs v ccio = +1.71v to +3v 0.65 x v ccio v ccio + 0.3 v ccio = +3v to +3.6v 2 v ccio + 0.3 high-level input voltage v ih rem input 2 v cc + 0.3 v v ccio = +1.71v to +3v 0 0.3 x v ccio v ccio = +3v to +3.6v 0 0.8 low-level input voltage v il rem input 0 0.8 v v in = 0 to v ccio v ccio = +1.71v to +3.6v -20 +20 input current i in v in = 0 to v cc, rem input -20 +20 ? input clamp voltage v cl i cl = -18ma -1.5 v single-ended outputs i oh = -100? v ccio - 0.1 high-level output voltage v oh i oh = -2ma v ccio - 0.35 v note 1: package thermal resistances were obtained using the method described in jdec specification jesd51-7, using a 4-layerboard. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . downloaded from: http:///
max9257/max9258 _______________________________________________________________________________________ 3 fully programmable serializer/deserializer with uart/i 2 c control channel max9257 dc electrical characteristics (continued)(v cc_ = +3.0v to +3.6v, r l = 50 ?%, t a = -40? to +105?, unless otherwise noted. typical values are at v cc_ = +3.3v, t a = +25?.) (notes 2, 3) parameter symbol conditions min typ max units i ol = 100? 0.1 low-level output voltage v ol i ol = 2ma 0.3 v shorted to gnd -44 -10 output short-circuit current i os shorted to v cc_ 10 44 ma i 2 c/uart i/o input leakage current i ilkg v i = v cc -1 +1 ? high-level input voltage sda/rx v ih2 0.7 x v cc v low-level input voltage sda/rx v il2 0.3 x v cc v low-level output voltagescl, sda v ol2 r pullup = 1.6k 0.4 v lvds outputs (sdo+, sdo-) differential output voltage v od 250 350 460 mv change in v od between complementary output states ? v od 20 mv common-mode voltage v os 1.050 1.25 1.375 v change in v os between complementary output states ? v os preemphasis off(figure 1) 20 mv output short-circuit current i os v sdo+ or v sdo- = 0 or 3.6v -15 +15 ma magnitude of differential outputshort-circuit current i osd v od = 0 15 ma control channel transceiver differential output voltage v od 250 350 460 mv v hyst+ differential low-to-high threshold 25 90 135 input hysteresis(figure 2) v hyst- differential high-to-low threshold -25 -90 -135 mv downloaded from: http:///
max9257/max9258 4 _______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel max9257 dc electrical characteristics (continued)(v cc_ = +3.0v to +3.6v, r l = 50 ?%, t a = -40? to +105?, unless otherwise noted. typical values are at v cc_ = +3.3v, t a = +25?.) (notes 2, 3) parameter symbol conditions min typ max units power supply ?% spread, preemphasis off,prate = 60mhz, srate = 840mbps 104 126 no spread, preemphasis off,prate = 60mhz, srate = 840mbps 99 121 n o sp r ead , p r eem p hasi s = 20%, p rate = 60m h z, s rate = 840m b p s 99 120 n o sp r ead , p r eem p hasi s = 60%, p rate = 60m h z, s rate = 840m b p s 108 127 n o sp r ead , p r eem p hasi s = 100%, p rate = 60m h z, s rate = 840m b p s 110 129 ?% spread, preemphasis off,prate = 28.57mhz, srate = 400mbps 78 96 no spread, preemphasis off,prate = 28.57mhz, srate = 400mbps 77 94 no spread, preemphasis = 100%,prate = 28.57mhz, srate = 400mbps 86 105 ?% spread, preemphasis off,prate = 14.29mhz, srate = 200mbps 55 68 no spread, preemphasis off,prate = 14.29mhz, srate = 200mbps 54 67 no spread, preemphasis = 100%,prate = 14.29mhz, srate = 200mbps 59 73 ?% spread, preemphasis off,prate = 7.14mhz, srate = 100mbps 44 55 no spread, preemphasis off,prate = 7.14mhz, srate = 100mbps 43 54 n o sp r ead , p r eem p hasi s = 100%, p rate = 7.14m h z, s rate = 100m b p s 46 57 ?% spread, preemphasis off,prate = 5mhz, srate = 70mbps 34 43 no spread, preemphasis off,prate = 5mhz, srate = 70mbps 34 42 worst-case supply current(figure 3) c l = 8pf, 12 bits i ccw no spread, preemphasis = 100%,prate = 5mhz, srate = 70mbps 36 45 ma sleep mode supply current i ccs sleep mode 92 ? downloaded from: http:///
max9257/max9258 _______________________________________________________________________________________ 5 fully programmable serializer/deserializer with uart/i 2 c control channel max9257 ac electrical characteristics (v cc_ = +3.0v to +3.6v, r l = 50 ?%, t a = -40? to +105?, unless otherwise noted. typical values are at v cc_ = +3.3v, t a = +25?.) (notes 5, 9) parameter symbol conditions min typ max units pclk_in timing requirements clock period t t 14.28 200.00 ns clock frequency f clk 1/t t 57 0 m h z clock duty cycle dc t high /t t or t low /t t 35 50 65 % clock transition time t r , t f (figure 7) 4 ns switching characteristics lvds output rise time t r 20% to 80% (figure 4) 315 370 ps lvds output fall time t f 20% to 80% (figure 4) 315 370 ps t r1a , t f1a 642 970 1390 t r2 , t f2 810 1140 1420 control transceiver transitiontime t r1b , t f1b 20% to 80% (figure 16) 290 386 490 ps input setup time t s (figure 5) 0 ns input hold time t h (figure 5) 3 ns t psd1 spread off (figure 6) (4.55 x t t ) + 11 parallel-to-serial delay t psd2 ?% spread ( 36.55 x t t ) + 11 ns pll lock time t lock combined fpll and spll; pclk_in stable 32,768 x t t ns random jitter t rj 420mhz lvds output, spread off,fpll = bypassed 12 ps (rms) deterministic jitter t dj 2 18 - 1 prbs, srate = 840mbps, 18 bits, no spread 142 ps (p-p) scl/tx, sda/rx r pullup = 10k 400 rise time t rs 0.3 x v cc to 0.7 x v cc , c l = 30pf r pullup = 1.6k 60 ns fall time t fs 0.7 x v cc to 0.3 x v cc, c l = 30pf 40 ns 95kbps to 400kbps 100 400kbps to 1000kbps 50 1000kbps to 4250kbps 10 pulse width of spike suppressedin sda t spk dc to 10mbps (bypass mode) 10 ns 400kbps 100 data setup time t setup 4.25mbps, c l = 10pf 60 ns 400kbps 100 data hold time t hold 4.25mbps, c l = 10pf 0 ns i 2 c timing (note 8) maximum scl clock frequency f scl 4.25 mhz minimum scl clock frequency f scl 95 khz start condition hold time t hd:sta (figure 30) 0.6 s downloaded from: http:///
max9257/max9258 6 _______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel max9257 ac electrical characteristics (continued)(v cc_ = +3.0v to +3.6v, r l = 50 ?%, t a = -40? to +105?, unless otherwise noted. typical values are at v cc_ = +3.3v, t a = +25?.) (notes 5, 9) parameter symbol conditions min typ max units low period of scl clock t low (figure 30) 1.1 s high period of scl clock t high (figure 30) 0.6 s repeated start conditionsetup time t su:sta (figure 30) 0.5 s data hold time t hd:dat (figure 30) 0 0.9 ? data setup time t su:dat (figure 30) 100 ns setup time for stop condition t su:sto (figure 30) 0.5 s bus free time t buf (figure 30) 1.1 s max9258 dc electrical characteristics(v cc_ = +3.0v to +3.6v, r l = 50 ?%, differential input voltage |v id | = 0.05v to 1.2v, input common-mode voltage v cm = |v id /2| to v cc - |v id /2|, t a = -40? to +105?, unless otherwise noted. typical values are at v cc_ = +3.3v, |v id | = 0.2v, v cm = 1.2v, t a = +25?.) (notes 2, 3) parameter symbol conditions min typ max units single-ended inputs high-level input voltage v ih 2.0 v cc v low-level input voltage v il 00 . 8 v txin -60 +60 input current i in v in = 0 to v cc pd -20 +20 ? input clamp voltage v cl i cl = -18ma -1.5 v single-ended outputs i oh = -100? v ccout - 0.1 high-level output voltage v oh i oh = -2ma v ccout - 0.35 v i ol = 100? 0.1 low-level output voltage v ol i ol = 2ma 0.3 v high-impedance output current i oz pd = low, v o = 0 to v ccout -1 +1 ? v o = 0v (note 4) -16 -65 output short-circuit current i os pclk_out, v o = 0v -22 -80 ma open-drain outputs output low voltage v ol v ccout = +3v, i ol = 6.4ma 0.55 v output low voltage v ol v ccout = +1.71v, i ol = 1.95ma 0.3 v leakage current i leak v o = 0 or v cc 1 a lvds inputs (sdi+, sdi-) differential input high threshold v th 50 mv differential input low threshold v tl -50 mv input current i in+ , i in- -60 +60 ? power-off input current i ino+ , i ino- v cc_ = 0 or open -70 +70 ? control channel transceiver differential output voltage v od 250 460 mv downloaded from: http:///
max9257/max9258 _______________________________________________________________________________________ 7 fully programmable serializer/deserializer with uart/i 2 c control channel max9258 dc electrical characteristics (continued)(v cc_ = +3.0v to +3.6v, r l = 50 ?%, differential input voltage |v id | = 0.05v to 1.2v, input common-mode voltage v cm = |v id /2| to v cc - |v id /2|, t a = -40? to +105?, unless otherwise noted. typical values are at v cc_ = +3.3v, |v id | = 0.2v, v cm = 1.2v, t a = +25?.) (notes 2, 3) parameter symbol conditions min typ max units v hyst+ differential low-to-high threshold 25 90 135 input hysteresis(figure 2) v hyst- differential high-to-low threshold -25 -90 -135 mv power supply ?% spread, prate = 60mhz,srate = 840mbps 85 128 spread off, prate = 60mhz,srate = 840mbps 71 115 ?% spread, prate = 28.57mhz,srate = 400mbps 67 102 spread off, prate = 28.57mhz,srate = 400mbps 57 84 ?% spread, prate = 14.29mhz,srate = 200mbps 55 82 spread off, prate = 14.29mhz,srate = 200mbps 46 67 ?% spread, prate = 5mhz,srate = 70mbps 42 57 worst-case supply currentc l = 8pf, 12 bits (figure 8) i ccw spread off, prate = 5mhz,srate = 70mbps 34 49 ma power-down supply current i ccz pd = low 10 50 a max9258 ac electrical characteristicsv cc_ = +3.0v to +3.6v, r l = 50 ?%, c l = 8pf, differential input voltage |v id | = 0.1v to 1.2v, input common-mode voltage v cm = |v id /2| to v cc - |v id /2|, t a = -40? to +105?, unless otherwise noted. typical values are at v cc_ = +3.3v, |v id | = 0.2v, v cm = 1.2v, t a = +25?. (notes 5, 6, and 7) parameter symbol conditions min typ max units switching characteristics output transition time t r, t f (figure 9) 0.7 2.2 ns output transition time,pclk_out t r, t f (figure 9) 0.5 1.5 ns output transition time t r, t f v ccout = 1.71v (figure 9) 1.0 2.8 ns output transition time,pclk_out t r, t f v ccout = 1.71v (figure 9) 0.7 2.2 ns control channel transition time t r1a, t f1a, t r1b , t f1b (figure 16) 0.5 1.2 ns control channel transition time t r2, t f2 (figure 16) 0.6 1.3 ns pclk_out high time t high (figure 10) 0.4 x t t 0.6 x t t ns pclk_out low time t low (figure 10) 0.4 x t t 0.6 x t t ns downloaded from: http:///
max9257 supply current vs. frequency max9257/58 toc01 pclk frequency (mhz) supply current (ma) 20 40 25 35 15 30 10 20 40 60 80 100 120 0 54 5 prbs pattern18-bit 100% preemphasis no preemphasis max9257 supply current vs. frequency max9257/58 toc02 pclk frequency (mhz) supply current (ma) 55 15 45 6040 20 80 100 120 140 0 57 5 35 65 25 prbs pattern10-bit 100% preemphasis no preemphasis max9258 supply current vs. frequency max9257/58 toc03 pclk frequency (mhz) supply current (ma) 40 10 35 15 4020 60 80 100 120 0 54 5 25 20 30 prbs pattern18-bit 4% spread no spread typical operating characteristics (v cc_ = +3.3v, r l = 50 , c l = 8pf, t a = +25?, unless otherwise noted.) max9257/max9258 8 _______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel max9258 ac electrical characteristics (continued)v cc_ = +3.0v to +3.6v, r l = 50 ?%, c l = 8pf, differential input voltage |v id | = 0.1v to 1.2v, input common-mode voltage v cm = |v id /2| to v cc - |v id /2|, t a = -40? to +105?, unless otherwise noted. typical values are at v cc_ = +3.3v, |v id | = 0.2v, v cm = 1.2v, t a = +25?. (notes 5, 6, and 7) parameter symbol conditions min typ max units data valid before pclk_ out t dvb (figure 11) 0.35 x t t ns data valid after pclk_out t dva (figure 11) 0.35 x t t ns t spd1 spread off (figure 14) 8t t serial-to-parallel delay t spd2 ?% spread 40t t ns power-up delay t pud (figure 12) 100 ns power-down to high impedance t pdd (figure 13) 100 ns jitter tolerance t jt each half of the ui, 12 bit,srate = 840mbps, prbs pattern (figure 15) no spread 0.25 0.30 ui note 2: current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to groundexcept v th and vtl. note 3: maximum and minimum limits over temperature are guaranteed by design and characterization. devices are productiontested at t a = +105?. note 4: one output at a time. note 5: ac parameters are guaranteed by design and characterization, and are not production tested. note 6: c l includes probe and test jig capacitance. note 7: t t is the period of the pclk_out. note 8: for high-speed mode timing, see the detailed description section. note 9: i 2 c timing parameters are specified for fast-mode i 2 c. max data rate = 400kbps. downloaded from: http:///
max9257/max9258 _______________________________________________________________________________________ 9 max9258 supply current vs. frequency max9257/58 toc04 pclk frequency (mhz) supply current (ma) 40 10 35 15 4020 60 80 100 120 0 54 5 25 20 30 prbs pattern10-bit 4% spread no spread serial link switching pattern without preemphasis (bit rate = 840mhz, 2m stp cable) max9257/58 toc05 max9257/58 toc06 serial link switching pattern with preemphasis (bit rate = 840mhz, 2m stp cable) (preemphasis = 100%) max9257 output power spectrum vs. pclk frequency max9257/58 toc07 pclk frequency (mhz) output power spectrum (dbm) 21 19 -20-30 -10 0 -60-70 -50 -40 10 20 -80 18 22 20 10khz bw 4% spread 2% spread no spread max9257 output power spectrum vs. pclk frequency max9257/58 toc08 pclk frequency (mhz) output power spectrum (dbm) 44 40 -20 0 -60 -40 20 -80 38 46 42 10khz bw 1.5% spread 2% spread no spread max9258 output power spectrum vs. pclk frequency max9257/58 toc09 pclk frequency (mhz) output power spectrum (dbm) 44 40 -20 0 -60 -40 20 -80 38 46 42 10khz bw 4% spread 2% spread no spread bit error rate (< 10 -9 ) vs. cable length max9257/58 toc10 cable length (m) serial-data rate (mbps) 700 800500 600 900400 08 6 2 4 10 12 14 16 18 20 ber can be as low as 10 -12 for cable lengths less than 10m. no spreadstp cable no preemphasis 100% preemphasis bit error rate (< 10 -9 ) vs. cable length max9257/58 toc11 cable length (m) serial-data rate (mbps) 700 800500 600 900400 08 6 2 4 10 12 14 16 18 20 ber can be as low as 10 -12 for cable lengths less than 10m. 2% spread onmax9257, stp cable no preemphasis 100% preemphasis typical operating characteristics (continued) (v cc_ = +3.3v, r l = 50 , c l = 8pf, t a = +25?, unless otherwise noted.) fully programmable serializer/deserializer with uart/i 2 c control channel downloaded from: http:///
max9257/max9258 10 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel max9257 pin description pin tqfn lqfp name function 1, 18 2, 21 v ccio single-ended input/output buffer supply voltage. bypass v ccio to gnd with 0.1? and 0.001? capacitors in parallel as close as possible to the device with the smallest valuecapacitor closest to v ccio . 2, 11, 19, 34 3, 14, 22, 41 gnd digital supply ground 3? 4? din[9:14]/ gpio[1:6] data input/general purpose input/output. when a serial-data word is less than 18 bits word length, din_ not programmed as data inputs becomes gpio (table 22). din[9:14] are internally pulled down to ground. 9 10 gnd fpll filter pll ground 10 11 v ccfpll filter pll supply voltage. bypass v ccfpll to gnd fpll with 0.1? and 0.001? capacitors in parallel as close as possible to the device with the smallest value capacitor closest tov ccfpll . 12 15 din15/gpio7 data input/general purpose input/output. when a serial-data word is less than 18 bits word length, din_ not programmed as data input becomes gpio (table 22). din15 is internally pulled down to ground. 13 16 hsync_in horizontal sync input. hsync_in is internally pulled down to ground. 14 17 vsync_in vertical sync input. vsync_in is internally pulled down to ground. 15 18 pclk_in parallel clock input. pclk_in latches data and sync inputs and provides the pll referenceclock. pclk_in is internally pulled down to ground. 16 19 scl/tx o p en- d r ai n c ontr ol c hannel outp ut. s c l/tx b ecom es s c l outp ut w hen u art- to- i 2 c i s acti ve. s c l/tx b ecom es tx outp ut w hen u art- to- i 2 c i s b yp assed . e xter nal l y p ul l up to v c c . 17 20 sda/rx open-drain control channel input/output. sda/rx becomes bidirectional sda when uart-to-i 2 c is active. sda/rx becomes rx input when uart-to-i 2 c is bypassed. sda output requires a pullup to v cc . 20, 33 23, 40 v cc digital supply voltage. bypass v cc to ground with 0.1? and 0.001? capacitors in p ar al l el as cl ose as p ossi b l e to the d evi ce w i th the sm al l est val ue cap aci tor cl osest to v c c . 21 26 gpio8 general purpose input/output 22 27 gpio9 general purpose input/output 23 28 v ccspll spread pll supply voltage. bypass v ccspll to gnd spll with 0.1? and 0.001? capacitors in parallel as close as possible to the device with the smallest value capacitorclosest to v ccspll . 24 29 gnd spll spll ground 25 30 gnd lvds lvds ground 26 31 sdo- serial lvds inverting output 27 32 sdo+ serial lvds noninverting output 28 33 v cclvds lvds supply voltage. bypass v cclvds to gnd lvds with 0.1? and 0.001? capacitors in parallel as close as possible to the device with the smallest value capacitor closest tov cclvds . downloaded from: http:///
max9257/max9258 ______________________________________________________________________________________ 11 fully programmable serializer/deserializer with uart/i 2 c control channel max9257 pin description (continued) pin tqfn lqfp name function 29 34 rem remote power-up/power-down select input. connect rem to ground for power-up tofollow v cc . connect rem high to v cc through 10k resistor for remote power-up. rem is internally pulled down to gnd. 30, 31, 32, 35?9 35, 38, 39, 42?6 din[0:7] data inputs. din[0:7] are internally pulled down to ground. 40 47 din8/gpio0 data input/general purpose input/output. when a serial-data word is less than 18 bits word length, din_ not programmed as data input becomes gpio (table 22). din8 is internally pulled down to ground. 1, 12, 13 24, 25, 36, 37, 48 n.c. no connection. not internally connected. ep exposed pad for thin qfn package only. connect ep to ground. max9258 pin description pin name function 1, 12, 13, 24, 25, 36, 37 n.c. no connection. not internally connected. 2v cc digital supply voltage. bypass v cc to gnd with 0.1? and 0.001? capacitors in parallel as close as possible to the device with the smallest value capacitor closest v cc . 3, 14 gnd digital supply ground 4 pd lvcmos/lvttl power-down input. drive pd high to power up the device and enable all outputs. drive pd low to put all outputs in high impedance and reduce supply current. pd is internally pulled down to ground. 5v cclvds lvds supply voltage. bypass v cclvds to gnd lvds with 0.1? and 0.001? capacitors in parallel as close as possible to the device with the smallest value capacitor closest to v cclvds . 6 sdi- serial lvds inverting input 7 sdi+ serial lvds noninverting input 8 gnd lvds lvds supply ground 9 gnd pll pll supply ground 10 v ccpll pll supply voltage. bypass v ccpll to gnd pll with 0.1? and 0.001? capacitors in parallel as close to the device as possible with the smallest value capacitor closest to v ccpll . 11 error active-low, open-drain error output. error asserts low to indicate a data transfer error was detected (parity, prbs, or uart control channel error). error is high to indicate no error detected. error resets when the error registers are read for parity, control channel errors, and when prbs enable bit is reset for prbs errors. pull up to v ccout with a 1k resistor. 15 rx lvcmos/lvttl control channel uart output downloaded from: http:///
max9257/max9258 12 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel max9258 pin description (continued) pin name function 16 tx lvcmos/lvttl control channel uart input. tx is internally pulled up to v ccout . 17 lock open-drain lock output. lock asserts high to indicate plls are locked with correct serial-word boundary alignment. lock asserts low to indicate plls are not locked or incorrect serial-word boundary alignment was detected. pull up to v ccout with a 1k resistor. 18 pclk_out lvcmos/lvttl recovered clock output 19 vsync_out lvcmos/lvttl vertical sync output 20 hsync_out lvcmos/lvttl horizontal sync output 21, 28?5, 40?6 dout[15:0] lvcmos/lvttl data outputs 22, 39 v ccout output supply voltage. v ccout is the supply for all output buffers. bypass v ccout to gnd out with 0.1? and 0.001? capacitors in parallel as close as possible to the device with the smallest valuecapacitor closest to v ccout . 23, 38, 48 gnd out output supply ground 26 v ccspll spread-spectrum pll supply voltage. bypass v ccspll to gnd spll with 0.1? and 0.001? capacitors in parallel as close as possible to the device with the smallest value capacitor closest tov ccspll . 27 gnd spll spll ground 47 ccen lvcmos/lvttl control channel enabled output. ccen asserts high to indicate that controlchannel is enabled. downloaded from: http:///
max9257/max9258 ______________________________________________________________________________________ 13 fully programmable serializer/deserializer with uart/i 2 c control channel sdo- v od v os gnd r l /2 r l /2 sdo+ sdo- sdo+ (sdo+) - (sdo-) v os (-) v os (+) ((sdo+) + (sdo-))/2 v os (-) v od (-) v od (-) v od = 0v ? v os = | v os (+) - v os (-) | ? v od = | v od (+) - v od (-) | v od (+) figure 1. max9257 lvds dc output parameters v id = 0v +v id -v id v out v hyst+ v hyst- figure 2. input hysteresis pclk_in note: pclk_in programmed for rising latch edge. din figure 3. max9257 worst-case pattern input downloaded from: http:///
max9257/max9258 14 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel sdo- c l c l r l sdo+ t fall 20% 20% (sdo+) - (sdo-) 80% 80% t rise figure 4. max9257 lvds control channel output load and output rise/fall times v ihmin v ihmin v ihmin v ilmax v ilmax v ilmax pclk_in din, vsync_in, hsync_in t hold t set note: pclk_in programmed for rising latching edge. figure 5. max9257 input setup and hold times downloaded from: http:///
max9257/max9258 ______________________________________________________________________________________ 15 fully programmable serializer/deserializer with uart/i 2 c control channel t psd1 first bit last bit n n+3 expanded time scale n+4 n n+1 n+2 n-1 din, hsync_in, vsync_in pclk_in sdo figure 6. max9257 parallel-to-serial delay v ilmax t high t low t t t r t f v ihmin pclk_in figure 7. max9257 parallel input clock requirements pclk_out dout note: pclk_out programmed for rising latch edge. figure 8. max9258 worst-case pattern output 0.9 x v ccout 0.1 x v ccout t f t r c l single-ended output load max9258 figure 9. max9258 output rise and fall times downloaded from: http:///
max9257/max9258 16 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel v olmax t high t low t t v ohmin pclk_out figure 10. max9258 clock output high and low time pclk_out t dvb t dva v ohmin v olmax v ohmin v olmax note: pclk_out programmed for rising latching edge. dout, vsync_out,hsync_out, lock figure 11. max9258 output data valid times pd powered down t pud powered up (outputs active) v ihmin figure 12. max9258 power-up delay pd high impedance dout, vsync, hsync powered down powered up t pdd v ilmax figure 13. max9258 power-down delay downloaded from: http:///
max9257/max9258 ______________________________________________________________________________________ 17 fully programmable serializer/deserializer with uart/i 2 c control channel first bit sdi pclk_out dout, hsync_out, vsync_out last bit serial word n serial-word length serial word n+1 serial word n+2 t spd1 parallel word n-2 parallel word n-1 parallel word n note: pclk_out programmed for rising latching edge. figure 14. max9258 serial-to-parallel delay 1.0ui 0.75ui 0.50ui 0.25ui 0.0ui t jt t s t s t jt +25mv -25mv +100mv 0v -100mv input template for lvds serial v sdi+ - v sdi- note: ui is one serial bit. time input is measured differentially (v sdi+ - v sdi- ). t r1a t f1b t r1b t f1a (sdo+) - (sdo-) 0.8v od(+) t f2 t r2 0.8 x | v od(+) + v od(-) | 0.8 x | v od(+) + v od(-) | 0.2v od(-) 0.8v od(-) 0.2v od(-) 0.8v od(-) 0.2 x | v od(+) + v od(-) | 0.2 x | v od(+) + v od(-) | 1 0 0.2v od(+) 0.8v od(+) 0.2v od(+) figure 15. max9258 jitter tolerance figure 16. control channel transition time downloaded from: http:///
max9257/max9258 detailed description the max9257 serializer pairs with the max9258 deseri-alizer to form a complete digital video serial link. the electronic control unit (ecu) programs the registers in the max9257, max9258, and peripheral devices, such as a camera, during the control channel phase that occurs at startup or during the vertical blanking time. all control channel communication is half-duplex. the uart communication between the max9258 and the max9257 is encoded to allow transmission through ac- coupling capacitors. the max9257 communicates to the peripheral device through uart or i 2 c. the max9257/max9258 dc-balanced serializer anddeserializer operate from a 5mhz-to-70mhz parallel clock frequency, and are capable of serializing and deserializing programmable 10, 12, 14, 16, and 18 bitsparallel data during the video phase. the max9257/ max9258 have two phases of operation: video and control channel (figures 19 and 20). during the video phase, the max9257 accepts parallel video data and transmits serial encoded data over the lvds link. the max9258 accepts the encoded serial lvds data and converts it back to parallel output data. the max9257 has dedicated inputs for hsync and vsync. the selected vsync edge causes the max9257/max9258 to enter the control channel phase. nonactive vsync edge can be asserted after eight pixel clock cycles. the video data are coded using two overhead bits (en0 and en1) resulting in a serial-word length of n+2 bits. the max9257/max9258 feature programmable 18 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel max9258 i 2 c uart- to-i 2 c uart uart camera ecu deserializer max9257 serializer video data pixel clock lock hsync_out vsync_out rx tx error pd ccen video data pixel clock hsync_in vsync_in sda scl gpio 100 100 figure 17. serial link with i 2 c camera programming interface (base mode) max9258 uart uart uart uart camera ecu deserializer max9257 serializer video data pixel clock hsync_out vsync_out rx tx error pd ccen lock video data pixel clock hsync_in vsync_in rx tx gpio 100 100 figure 18. serial link with uart camera programming interface (bypass mode) downloaded from: http:///
parity encoding that adds two parity bits to the serialword. bit 0 (en0) is the lsb that is serialized first with- out parity enabled. the parity bits are serialized first when parity is enabled. the ecu programs the max9258, max9257, and peripheral devices at startup and during the control channel phase. in a digital video system, the control channel phase occurs during the vertical blanking time and synchronizes to the vsync signal. the programma- ble active edge of vsync initiates the control channel phase. nonactive edge of vsync can transition at any time after 8 x t t if max9257 spread is not enabled and 0.5/f ssm when enabled. at the end of video phase, the max9258 drives ccen high to indicate to the ecu that the control channel is open. programmable tim ers and ecu signal activity determine how long the controlchannel stays open. the timers are reset by ecu signal activity. ecu programming must not exceed the vertical blanking time to avoid loss of video data. after the control channel phase closes, the max9257 sends a 546 or 1090 word pattern as handshaking (hsk) to synchronize the max9258? internal clock recovery circuit to the max9257? transmitted data. following the handshaking, the control channel is closed and the video phase begins. the serial lvds data is recovered and parallel data is valid on the pro- grammed edge of the recovered pixel clock. max9257/max9258 ______________________________________________________________________________________ 19 fully programmable serializer/deserializer with uart/i 2 c control channel video video hsk control vsync_in sdi/o sdi/o ccen hsk = handshaking 0.5/f ssm (max) spread profile figure 20. video and control channel phases (max9257 spread is enabled) video video hsk control vsync_in sdi/o sdi/o ccen hsk = handshaking 8t t figure 19. video and control channel phases (spread off) downloaded from: http:///
max9257/max9258 20 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel register name register address (hex) power-up value (hex) power-up default settings reg0 0x00 0xb5 prate = 10, 20mhz to 40mhzsrate = 11, 400mbps to 840mbps paren = 0, parity disabled pwidth = 101, parallel data width = 18 reg1 0x01 0x1f spread = 000, spread = offreserved = 11111 reg2 0x02 0xa0 stodiv = 1010, sto clock is pixel clock divided by 1024stocnt = 0000, sto counter counts to 1 reg3 0x03 0xa0 etodiv = 1010, eto clock is pixel clock divided by 1024etocnt = 0000, eto counter counts to 1 reg4 0x04 1) rem = 0, 0x282) rem = 1, 0x30 vedge = 0, vsync active edge is fallingreserved = 0 ckedge = 1, pixel clock active edge is rising pd: 1) if rem = 0, pd = 0 2) if rem = 1, pd = 1 seren: 1) if rem = 0, seren = 1 2) if rem = 1, seren = 0 bypfpll = 0, filter pll is active reserved = 0 prbsen = 0, prbs test disabled reg5 0x05 0xfa max9257 address = 1111 1010 reg6 0x06 0xff end frame = 1111 1111 reg7 0x07 0xf8 max9258 address = 1111 1000 reg8 0x08 0x00 intmode = 0, interface with peripheral is uartinten = 0, interface with peripheral is disabled fast = 0, uart bit rate = dc to 4.25mbps cto = 000, never come back bitrate = 00, base mode bit rate = 95kbps to 400kbps reg9 0x09 0x00 prbslen = 0000, prbs word length = 2 21 gpio9dir = 0, gpio9 = inputgpio8dir = 0, gpio8 = input gpio9 = 0 gpio8 = 0 reg10 0x0a 0x00 gpio7dir = 0, gpio7 = inputgpio6dir = 0, gpio6 = input gpio5dir = 0, gpio5 = input gpio4dir = 0, gpio4 = input gpio3dir = 0, gpio3 = input gpio2dir = 0, gpio2 = input gpio1dir = 0, gpio1 = input gpio0dir = 0, gpio0 = input table 1. max9257 power-up default register map (see the max9257 register table ) downloaded from: http:///
max9257/max9258 ______________________________________________________________________________________ 21 fully programmable serializer/deserializer with uart/i 2 c control channel register name register address (hex) power-up value (hex) power-up default settings reg11 0x0b 0x00 gpio7 = 0gpio6 = 0 gpio5 = 0 gpio4 = 0 gpio3 = 0 gpio2 = 0 gpio1 = 0 gpio0 = 0 reg12 0x0c 0xe0 preemp = 111, preemphasis = 0%reserved = 00000 reg13 0x0d 0x00 reserved = 000000i2cfilt = 00, i 2 c glitch filter settings: 1) 95kbps to 400kbps = 100ns2) 400kbps to 1000kbps = 50ns 3) 1000kbps to 4250kbps = 10ns reg14 0x0e 0x00 reserved = 0000 000locked = read only table 1. max9257 power-up default register map (continued) register name register address (hex) power-up value (hex) power-up default settings reg0 0x00 0xb5 prate = 10, 20mhz to 40mhzsrate = 11, 400mbps to 840mbps paren = 0, parity disabled pwidth = 101, parallel data width = 18 reg1 0x01 0x00 spread = 00, spread spectrum = offaer = 0, error count is reset by reading error registers reserved = 0 0000 reg2 0x02 0xa0 stodiv = 1010, sto clock is pixel clock divided by 1024stocnt = 0000, sto counter counts to 1 reg3 0x03 0xa0 etodiv = 1010, eto clock is pixel clock divided by 1024etocnt = 0000, eto counter counts to 1 reg4 0x04 0x20 vedge = 0, vsync active edge is fallinghedge = 0, hsync active edge is falling ckedge = 1, pixel clock active edge is rising reserved = 0000 prbsen = 0, prbs test disabled reg5 0x05 0xf8 max9258 address = 1111 1000 reg6 0x06 0xff end frame = 1111 1111 reg7 0x07 0x00 intmode = 0, interface with peripheral is uartinten = 0, interface with peripheral is disabled fast = 0, uart bit rate = dc to 4.25mbps cto = 000, never come back bitrate = 00, base mode bit rate = 95kbps to 400kbps table 2. max9258 power-up default register map (see the max9258 register table ) downloaded from: http:///
max9257/max9258 tables 1 and 2 show the default power-up values forthe max9257/max9258 registers. tables 3 and 4 show the input and output supply references. parallel-word width the parallel-word width is made up of the video databits, hsync, and vsync. the video data bits are pro- grammable from 8 to 16 depending on the pixel clock, serial-data rate, and parity. table 16 shows the parallel- word width. serial-word length the serial-word length is made up of the parallel-wordwidth, encoding bits, and parity bits. tables 5? show the serial video format and serial-word lengths without parity. tables 10?3 show with parity bits included. lvds serial data serial lvds data is transmitted least significant bit (lsb)to most significant bit (msb) as shown in tables 5 through 13. the ecu at startup can program the parallel word width, serial frequency range, parity, spread-spec-trum, and pixel clock frequency range ( see the max9257 register table and the max9258 register table) . 22 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel register name register address (hex) power-up value (hex) power-up default settings reg8 0x08 0x10 pathrlo = 0001 0000parity threshold = 16 reg9 0x09 0x00 pathrhi = 0000 0000,parity threshold = 16 reg10 0x0a 0x00 parity errors video (8 lsbs) = read only reg11 0x0b 0x00 parity errors video (8 msbs) = read only reg12 0x0c 0x00 prbs bit errors = read only reg13 0x0d 0x00 reserved = 000parity error, communication with max9258 = read only frame error, communication with max9258 = read only parity error, communication with max9257 = read only frame error, communication with max9257 = read only i 2 c error, communication with peripheral = read only table 2. max9258 power-up default register map (continued) inputs/outputs supply pclk_in, hsync_in, vsync_in,din[0:7], din[8:15]/gpio[0:7], gpio8, gpio9 v ccio sdo+, sdo- v cclvds scl/tx, sda/rx, rem v cc table 3. max9257 i/o supply inputs/outputs supply all inputs and outputs v ccout sdi+, sdi- v cclvds table 4. max9258 i/o supply downloaded from: http:///
max9257/max9258 ______________________________________________________________________________________ 23 fully programmable serializer/deserializer with uart/i 2 c control channel bit 1 2 34 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 name en0 en1 hsync vsync d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 table 5. serial video data format for 20-bit serial-word length (parallel-word width = 18) bit 12 3 4 5 6 7 8 9 1011121314151617 18 name en0 en1 hsync vsync d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 table 6. serial video data format for 18-bit serial-word length (parallel-word width = 16) bit 12 3 4 56789 10 11 12 13 14 15 16 name en0 en1 hsync vsync d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 table 7. serial video data format for 16-bit serial-word length (parallel-word width = 14) bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 name en0 en1 hsync vsync d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 table 8. serial video data format for 14-bit serial-word length (parallel-word width = 12) bit 1234 5 6 7 8 9 1 01 11 2 name en0 en1 hsync vsync d0 d1 d2 d3 d4 d5 d6 d7 table 9. serial video data format for 12-bit serial-word length (parallel-word width = 10) bit 1 2 3 4 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 name pr prb en0 en1 hsync vsync d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 table 10. format for 20-bit serial-word length with parity (parallel-word width = 16) bit 1 234 5 6 7 8 9 10111213141516 17 18 name pr prb en0 en1 hsync vsync d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 table 11. format for 18-bit serial-word length with parity (parallel-word width = 14) bit 1 234 5 6 789 10 11 12 13 14 15 16 name pr prb en0 en1 hsync vsync d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 table 12. format for 16-bit serial-word length with parity (parallel-word width = 12) bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 name pr prb en0 en1 hsync vsync d0 d1 d2 d3 d4 d5 d6 d7 table 13. format for 14-bit serial-word length with parity (parallel-word width = 10) downloaded from: http:///
max9257/max9258 pixel clock frequency range the max9257/max9258 each have registers that canbe configured at startup. depending on the word length, the max9257 multiplies pclk_in (pixel clock) by 12, 14, 16, 18, or 20 using an internal pll to gener- ate the serial clock. use table 20 for proper selection of available pclk frequency and serial-data ranges. parallel data is serialized using the serial-clock and serialized bits are transmitted at the max9257 lvds outputs. the max9257/max9258 support a wide range for pclk_in (table 14). if the pixel clock frequency needs to change to a frequency outside the pro- grammed range, the ecu must program both the max9257 and the max9258 in the same control chan- nel session. serial-data rate range the word length and pixel clock is limited by the maxi-mum serial-data rate of 840mbps. the following formula shows the relation between word length, pixel clock, and serial clock: serial-word length x pixel clock = serial-data rate 840mbps for example, if pclk_in is 70mhz, the serial-wordlength has to be 12 bits including dc balance bits if parity is not enabled to keep the serial-data rate under 840mbps. if the serial-word length is 20 bits, the maxi- mum pclk_in frequency is 42mhz. the serial-data rate can vary from 60mbps to 840mbps and can be programmed at power-up (table 15). use table 20 for proper selection of available pclk frequency and serial data ranges. operating in the incorrect range for either the serial-data rate or pclk_in can result in excessive current dissipation and failure of the max9258 to lock to the max9257. lvds common-mode bias the output common-mode bias is 1.2v at the lvdsinputs on the max9258 and lvds outputs on the max9257. no external resistors are required to provide bias for ac-coupling the lvds inputs and outputs. lvds termination terminate the lvds link at both ends with the charac-teristic impedance of the transmission line (typically 100 differential). the lvds inputs and outputs are high impedance to gnd and differentially. spread-spectrum selection the max9257/max9258 each have spread-spectrumoptions. both should not be turned on at the same time. when the max9257 is programmed for spread spectrum, the max9258 tracks and passes the spread to its clockand data outputs. the max9257/max9258 are both center spread (figure 21). the control channel does not use spread spectrum, but has slower transition times. max9258 spread spectrum the max9258 features a programmable spread-spec-trum clock and data outputs for reduced emi. the sin- gle-ended data outputs are programmable for no spread, ?%, or ?% (see the typical operating characteristics ) around the recovered pixel clock fre- quency. the output spread is programmed in registerreg1[7:6]. table 17 shows the spread options, and table 18 shows the various modulation rates. max9257 spread spectrum the max9257 features programmable spread spectrumfor the lvds outputs. table 19 shows various spread options, and table 20 shows the various modulation rates. only one device (the max9257 or the max9258) should be programmed for spread spectrum at a time. if the max9257 is programmed for spread, the max9258 24 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel frequency (mhz) prate (reg0[7:6]) 5?0 00 10?0 01 20?0 10 40?0 11 table 14. max9257 pixel clock range(pclk_in) serial-data rate (mbps) srate (reg0[5:4]) 60?00 00 100?00 01 200?00 10 400?40 11 table 15. serial-data rate range parallel-word width pwidth (reg0[2:0]) 10 000 12 001 14 010 16 011 18 1xx table 16. parallel-word width downloaded from: http:///
tracks and passes the spread to the data and clock out-puts. the prate range of 00 and 01 (5mhz pclk 20mhz) supports all the spread options. the praterange of 10 and 11 (20mhz pclk 70mhz) requires that the spread be 2% or less. pixel clock jitter filter the max9257 has a pll to filter high-frequency pixelclock jitter on pclk_in. the fpll can be bypassed by writing 1 to reg4[2]. the fpll improves the max9258? data recovery by filtering out the high-fre- quency components from the pixel clock that the max9258 cannot track. the 3db bandwidth of the fpll is 100khz (typ). lvds output preemphasis (sdo) the max9257 features programmable preemphasiswhere extra current is added when the lvds outputs transition on the serial link. preemphasis provides addi- tional current to the normal drive current. for example, 20% preemphasis provides 20% greater current than the normal drive current. current is boosted only on the transitions and returns to the normal drive current after switching. select the preemphasis level to optimize the eye diagram. preemphasis boosts the high-frequency content of the lvds outputs to enable driving greater cable lengths. the amount of preemphasis is pro- grammed in reg12[7:5] (table 21). vsync, hsync, and pixel clock polarity pclk: the max9257 is programmable to latch data on either rising or falling edge of pclk. the polarity ofpclkout at the max9258 can be independent of the max9257 pclk active edge. the polarity of pclk can be programmed using reg4[5] of the max9257 and the max9258. vsync: the max9257 and the max9258 enter control channel on the falling edge of vsync. the default reg-ister settings are vsync active falling edge for both the max9257 and the max9258. if the vsync active edge is programmed for rising edge at the max9257, the max9258 vsync active edge must also be pro- grammed for rising edge to reproduce vsync rising edge at the max9258 output. however, matching the polarity of the vsync active edge between the max9257 and the max9258 is not a requirement for proper operation. hsync: hsync active-edge polarity is programmable for the max9258. general purpose i/os (gpios) the max9257 has up to 10 gpios available. gpio8and gpio9 are always available while gpio[0:7] are available depending on the parallel-word width (table 22). if gpios are not available, the corresponding gpio bits are not used. max9257/max9258 ______________________________________________________________________________________ 25 fully programmable serializer/deserializer with uart/i 2 c control channel frequency time f spread (max) f pclk_in f spread (min) 1/f ssm figure 21. simplified modulation profile for the max9257/max9258 prate (reg1[7:6]) spread (%) 00 off 01 ? 10 off 11 ? table 17. max9258 spread prate (reg1[7:6]) modulation rate f ssm range (khz) 00 pclk/312 16 to 32 01 pclk/520 19.2 to 38.5 10 pclk/1040 19.2 to 38.5 11 pclk/1248 32 to 56 table 18. max9258 modulation rate reg1[7:5] spread (%) 000 off 001 ?.5 010 ?.75 011 ? 100 off 101 ? 110 ?.5 111 ? table 19. max9257 lvds output spread downloaded from: http:///
max9257/max9258 a gpio can be programmed to drive an lvcmos logiclevel or to read a logic input. the register bit that sets the output level when the gpio is programmed as an output stores the input level when the gpio is pro- grammed as an input. open-drain outputs (lock, error ) lock and error are open-drain outputs that require a pullup resistor to an external supply. error asserts low when an error occurs and lock is high impedancewhen the max9258 is locked to the max9257 and remains high under the locked condition. when the devices are in shutdown, the channel is not locked and lock goes high impedance, is pulled high, and should be ignored. error is high impedance at shutdown and remains high. in choosing pullup resistors, there isa tradeoff between power dissipation and speed; 10k pullup should be sufficient. 26 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel serial-word length srate prate pclk range (mhz) modulation rate f ssm range (khz) 11 11 40?0 pclk/2728 14.7 to 25.7 11 10 33.3?0 pclk/1736 19.2 to 23.0 10 10 20?3.3 pclk/1612 12.4 to 20.7 10 01 16.6?0 pclk/992 16.7 to 20.2 01 01 10?6.6 pclk/1116 9.0 to 14.9 01 00 8.3?0 pclk/744 11.2 to 13.4 12 00 00 5?.3 pclk/868 5.8 to 9.6 11 11 40?0 pclk/2304 17.4 to 26.0 11 10 28.6?0 pclk/1728 16.6 to 23.1 10 10 20?8.6 pclk/1440 13.9 to 19.9 10 01 14.3?0 pclk/1008 14.2 to 19.8 01 01 10?4.3 pclk/1008 9.9 to 14.2 01 00 7.1?0 pclk/720 9.9 to 13.9 14 00 00 5?.1 pclk/720 6.9 to 9.9 11 11 40?2.5 pclk/1968 20.3 to 26.7 11 10 25?0 pclk/1640 15.2 to 24.4 10 10 20?5 pclk/1312 15.2 to 19.1 10 01 12.5?0 pclk/984 12.7 to 20.3 01 01 10?2.5 pclk/820 12.2 to 15.2 01 00 6.25?0 pclk/656 9.5 to 15.2 16 00 00 5?.25 pclk/656 7.6 to 9.5 11 11 40?6.6 pclk/1840 21.7 to 25.3 11 10 22.2?0 pclk/1472 15.1 to 27.2 10 10 20?2.2 pclk/1104 18.1 to 20.1 10 01 11.1?0 pclk/920 12.1 to 21.7 01 01 10?1.1 pclk/736 13.6 to 15.1 01 00 5.6?0 pclk/736 7.6 to 13.6 18 00 00 5?.6 pclk/552 9.1 to 10.1 11 11 40?2 pclk/1632 24.5 to 25.7 11 10 20?0 pclk/1632 12.3 to 24.5 10 01 10?0 pclk/1020 9.8 to 19.6 20 01 00 5?0 pclk/816 6.1 to 12.3 table 20. max9257 modulation rate downloaded from: http:///
the lock and error outputs can be wired in an and configuration if you have multiple serializers anddeserializers, or a single serializer fanned out to multi- ple deserializers through a repeater. for such situa- tions, wire the multiple lock outputs together and use a single pullup resistor to pull up all the lines high. lock is high if all the devices are locked. do the same thing for error ; error is low if any max9258 reports errors. base mode and bypass mode (basics) in the control channel phase, there are two modes: baseand bypass. in base mode, ecu always communicates using the max9257/max9258 uart protocol and com- munication with a peripheral device is performed in i 2 c by the max9257. packets not addressed to themax9257 or the max9258 get converted to i 2 c and passed to the peripheral device. similarly, i 2 c packets from the peripheral device get converted to uart pack-ets in the reverse direction. ecu can disable communi- cation to the peripheral device by writing a 0 to inten (reg8[6] in the max9257 and reg7[6] in the max9258). base mode is the default mode. bypass mode is entered by writing a 0 to intmode and 1 to inten (table 23). bypass mode is exited if there is no activity from ecu in the control channel for the duration of cto. when cto times out, inten reverts back to 0 and max9257/ max9258 revert back to base mode. to permanently stay in bypass mode, ecu can lock the cto timer or program cto to be longer than eto and sto. timers the max9257/max9258 feature three different timers.the start timeout (sto) and end timeout (eto) control the duration of the control channel. the come-back timeout (cto) controls the duration of bypass mode. sto timer the sto (start timeout) timer closes the control channel ifthe ecu does not start using the control channel within the sto timeout period. the sto timer is configured by max9257/max9258 ______________________________________________________________________________________ 27 fully programmable serializer/deserializer with uart/i 2 c control channel reg12[7:5] preemphasis (%) 000,101,110 20 001 40 010 60 011 80 100 100 111 0 table 21. preemphasis parallel-word width (n) gpios available 18 gpio[8:9] 16 gpio[6:9] 14 gpio[4:9] 12 gpio[2:9] 10 gpio[0:9] table 22. gpios vs. parallel-word width inten max9257 reg8[6], max9258 reg7[6] intmode max9257 reg8[7], max9258 reg7[7] mode 0x base mode,communication with peripheral is not enabled 11 base mode,communication with peripheral is enabled (i 2 c) 10 bypass mode,communication with max9257/ max9258 is not enabled, communication with peripheral is enabled (uart) table 23. selection of base mode orbypass mode reg2[7:4] stodiv 00xx 16 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16,384 1111 32,768 table 24. sto clock divide ratio downloaded from: http:///
max9257/max9258 register reg2 for both the max9257 and the max9258.the four bits of reg2[7:4] select the divide ratio (stodiv) for the sto clock as a function of the pixel clock (table 24). the timeout period is determined by counter bits reg2[3:0] that increment once every sto clock period. write to reg2[3:0] to determine the counter end time. the sto counter counts to the programmed stocnt + 1. the ecu must begin communicating before sto times out, otherwise, the control channel closes (figure 22). the sto timeout period is given by: for example: if the pixel clock frequency is set to 16mhz, stodiv is set to 1010 (stodiv = 1024), and stocnt is set to 1001 (stocnt = 9), the sto timer counts with 15.625khz sto clock (16mhz/1024) internally until it reaches 10 and timer expires. the t sto is equal to t t x 1024 x 10 = 640?. the default value for stodiv is 1024 while the default value for stocnt is 0. that means the sto timeout period is equal 1024 pixel clock cycles. activity from the ecu on the control channel shuts off the sto timer and starts the eto timer. eto timer the eto (end timeout) timer closes the control channelif the ecu stops communicating for the eto timeout period. configure register reg3[7:4] for both the max9257 and the max9258 to select the divide ratio (etodiv) for the eto clock as a function of the pixel clock (table 25). the timeout period is determined by t f stodiv stocnt sto clk = ? ? ? ? ? ? + 1 1 () 28 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel reg3[7:4] etodiv 00xx 16 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16,384 1111 32,768 table 25. eto clock divide ratio video video hsk vsync_in sdi/o ccen t1 t2 t3 tx rx dout_ frozen t1 = time to enter control channelt2 = sto timeout period t3 = control channel exit time due to sto hsk = handshaking between the max9257 and the max9258 figure 22. control channel closing due to sto timeout downloaded from: http:///
counter bits reg3[3:0] that increment once every etoclock period. write to reg3[3:0] to determine the counter end time. the eto counter counts to the pro- grammed etocnt + 1. any ecu activity resets the eto timer. when the ecu stops transmitting data for the eto timeout period, the control channel closes (figure 23). for example: if the pixel clock frequency is set to 16mhz, etodiv is set to 1010 (etodiv = 1024), and etocnt is set to 1001 (etocnt = 9), the eto timer counts with the 15.625khz eto clock (16mhz/1024) internally until it reaches 10 and timer expires. the t eto is equal to t t x 1024 x 10 = 640?. the default value for etodiv is 1024 while the default value for etocnt is 0. that means the eto timeout period is equal to 1,024 pixel clock cycles. closing the control channel after the max9257 detects the active vsync edge, itsends three synchronization words. once the max9258 sees the active vsync transition and detects three syn- chronization words, it enters the control channel phase and ccen goes high. there is a brief delay of t1 between the vsync transition and ccen transitioninghigh. the ecu is allowed to communicate when ccen is high. if the ecu does not communicate while ccen is high (figure 22), the link remains silent and sto starts counting towards its preset timeout counter value. if sto times out (t2), ccen transitions low and the con- trol channel closes. if the ecu communicates while ccen is high and before sto expires (figure 23), the sto timer is turned off and eto timer is enabled. the eto counter (etoc- nt+1) is reset to 0 whenever activity from ecu (base mode) or ecu and camera (bypass mode) is detected. as long as there is activity from ecu (base mode) or ecu and camera (bypass mode) on the link, the chan- nel does not close and the eto counter resets. after the ecu (base mode) or ecu and camera (bypass mode) ceases link activity, eto times out (t4), ccen transitions low, and the control channel closes. another way to close the control channel in base mode is for the ecu to send an end frame (ef) to close the control channel without waiting for eto to time out. whenever ef is received by both the max9257/ max9258, control channel closes immediately and ccen goes low. a synchronization frame must precede ef. end frame cannot be used in bypass mode. the control channel must close by ef to report errors back to the ecu. t f etodiv etocnt eto clk = ? ? ? ? ? ? + 1 1 () max9257/max9258 ______________________________________________________________________________________ 29 fully programmable serializer/deserializer with uart/i 2 c control channel video video hsk vsync_in sdi/o ccen t1 t4 (base mode) t5 tx rx dout_ frozen t1 = time to enter control channelt4 = eto timeout period t5 = control channel exit time due to eto hsk = handshaking between max9257 and max9258 ecu activity t4 (bypass mode) figure 23. control channel closing due to eto timeout downloaded from: http:///
max9257/max9258 after the control channel closes, there is a brief hand-shake period (t3 in figure 22 and t5 in figure 23) between the max9257 and the max9258. the max9258 sends a special lock frame to the max9257 to indicate if pll is still locked. the max9258 sends the lock frame if the number of decoding errors didn? exceed a threshold in the last lvds video phase ses- sion. the max9258 features a proprietary vco lock that prevents frequency drift while in the control chan- nel for extended periods of time. if max9257 receives the lock frame, it understands that the max9258 is in a locked state and sends a short training sequence. if the lock frame is not received by the max9257, it assumes that the max9258 is not locked and sends a long train- ing sequence. after the short or long training sequence is complete, the max9257 sends three special synchro- nization words before entering the video phase. training sequence is used to resynchronize the max9257/max9258 before the video phase starts. the max9257/max9258 control channel duration is independent of vsync. the control channel does not close when vsync deasserts, which allows the use of a vsync interrupt signal on vsync_in. the control channel must be closed by sto, eto, or ef. if the con- trol channel does not close before video data becomes available, video data can be lost. sto/eto timer programming sto and eto can be programmed given the values oft2, t4, and maximum values of t1, t3, and t5 (figures 22, 23): t t = pixel clock period, t uclk = uart period when spread spectrum is not enabled in max9257: max(t1) = 2.5? + (3 x t t ) + (4 x t uclk ) when spread spectrum is enabled in max9257: max(t1) = 2.5? + (1400 x t t ) + (4 x t uclk ) t2 = t sto t4 = t eto when pixel clock frequency range (prate) is 00 or 01: when pixel clock frequency range (prate) is 10 or 11: cto timer the cto (come-back timeout) timer temporarily or per-manently blocks programming to the max9257/ max9258 registers. cto keeps the max9257/ max9258 in bypass mode for the cto timeout period (table 26). bypass mode can only be exited when the cto timer expires. the cto timer uses the uart bit times for its counter. note that sto and eto timers use the pixel clock while cto uses the uart bit times. the uart period t uclk synchronizes with the uart bit times, which synchronize every time the sync frame is sent.when the cto timer times out, inten bit in both devices is set to 0 and the max9257/max9258 revert back to base mode. if communication with the max9257/max9258 is not needed after initial program- ming is complete, cto may be set to 000 (never come back). in this case, cto never expires and the max9257/max9258 stay in bypass mode until they are powered down. this prevents accidental programming of the max9257/max9258 while ecu communicates with the peripheral using a different uart protocol from the max9257/max9258 uart protocol. the overall cto timeout is calculated as follows: t cto = t uclk x cto max( ) ( t t tt sto t uclk 3 8 1090 20 = ? ? ? ? ? ? + ? ? ? ? ? ? + )) max( ) ( t t tt eto tu c 5 8 1090 20 = ? ? ? ? ? ? + ? ? ? ? ? ? + l lk ) max( ) ( ) t t tt sto t uclk 3 8 546 20 = ? ? ? ? ? ? + ? ? ? ? ? ? + m max( ) ( t t tt eto t uclk 5 8 546 20 = ? ? ? ? ? ? + ? ? ? ? ? ? + )) 30 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel max9257 reg2[7:4]max9258 reg3[7:4] counter using uart bit times 000 never come back (lockout) 001 16 010 32 011 48 100 64 101 80 110 96 111 112 table 26. cto counter timeout period downloaded from: http:///
assuming a uart bit rate of 2mbps, reg2[7:4],reg3[7:4] = 100 (table 26), cto = 64, cto timeout calculated as: t cto = (0.5?) 64 = 32? link power-up the max9258 powers up when the power-down inputpd goes high. after approximately 130?, ccen goes high, indicating the control channel is available. thisdelay is required because the analog circuitry has to fully wake up. there are two ways to power up the max9257. the max9257 powers up according to the state of rem. ecu powers up max9257 remotely (ecu sends command to power up) when rem is pulled to v cc . the max9257 powers up according to the supply voltage when rem is grounded. powering the max9257 with serialization enabled (rem = ground at power-up) when rem is grounded, the max9257 fully powers upwhen power is applied. the power-down bit pd (reg4[4]) is disabled and serialization bit seren (reg4[3]) is enabled. if pclk_in is not running, the max9257 stays in the control channel. after pclk_in is applied, the control channel times out due to sto, eto, or ef. the max9257 starts the handshaking after the max9257 locks to pclk after 32,768 clock cycles. if pclk_in is running, serialization starts automatically after pll of the max9257 locks to pclk_in with default values in the registers. remote power-up of the max9257 (rem = pulled up to v cc ) when rem is pulled up to v cc , the max9257 wakes up in a low power state, drawing less than 100? supplycurrent. to wake-up the max9257, the ecu first trans- mits a dummy frame 0xdb and then waits at least 100? to allow the max9257? internal analog circuitry to fully power up. then the ecu configures the max9257 registers, including a write to disable the pd bit (reg4[4]) so that the max9257 does not return back to the low power state. every packet needs to start with a synchronization frame (see the uart sec- tion). if the pd bit is not disabled within 70ms aftertransmitting the dummy frame, the max9257 returns to the low power state and the whole power-up sequence needs to be repeated. after configuration is complete, the ecu also needs to enable the seren bit to start the video phase. at initial power-up with rem pulled to v cc , default value of seren bit is 0, so sto and eto timers are not active.control channel is enabled as long as seren is 0. this allows the control channel to be used for extensive programming at initial power-up without the channeltiming out. uart, parity, framing and packet errors in the control channel communications are reported if end frame is used to close control channel (see the max9258 error checking and reporting section). for faster identification of errors, verify every write com-mand by reading back the registers before enabling serialization. link power-down when the control channel is open, the ecu writes to thepd bit to power down the max9257. in this case, to power up the max9257 again, the power-up sequence explained in the remote power-up of the max9257 (rem = pulled up to v cc ) section needs to be repeated. the max9258 has a pd input that powers down the device. max9258 error checking and reporting the max9258 has an open-drain error output. this output indicates various error conditions encounteredduring the operation of the system. when an error con- dition is detected and needs to be reported, error asserts low. error indicates three error conditions: uart, video parity, and prbs errors. uart errors during control channel communication in base mode,the max9257/max9258 record uart frame, parity, and packet errors. i 2 c errors are also recorded by max9257 when i 2 c interface is enabled. if ecu closes the control channel by using end frame (ef), themax9257 sends a special internal uart frame back to the max9258 called error frame. the max9257 uart and i 2 c errors are reset at the next control channel. the max9258 receives the error frame and records theerror status in its uart error register (reg13). ecu must use end frame to the close control channel for the max9257 to report back uart and i 2 c errors to the max9258. whenever one of the bits in the uart errorregister is 1, error asserts low. the uart error regis- ter is reset when ecu reads it, and error deasserts high immediately if uart errors were the only reasonthat error was asserted low. if the max9258 is not locked (lock = low), uart error is not reported. video parity errors when video parity check is enabled (reg0[3] in bothdevices), the max9258 counts the number of video pari- ty errors by checking recovered video words. value of this counter is reflected in paerrhi (8 msb bits, reg11) and paerrlo (8 lsb bits, reg10). if the num- ber of detected parity errors is greater than or equal to the parity error threshold pathrhi (reg9) and pathrlo (reg8), then error asserts low. in this max9257/max9258 ______________________________________________________________________________________ 31 fully programmable serializer/deserializer with uart/i 2 c control channel downloaded from: http:///
max9257/max9258 case, error deasserts high after next video phase starts if video parity errors were the only reason thaterror was asserted low. to report parity errors in bypass mode, program autoerror reset (aer) to 1(reg1[5] = 1). autoerror reset the default method to reset errors is to read the respec-tive error registers in the max9258 (registers 10, 11, and 13). if errors were present before the next control chan- nel, the error count gets incremented to the previous number. by setting the autoerror reset (aer) bit to 1, the error registers reset when the control channel ends. setting aer to 1 does not reset prbs errors. prbs errors during the prbs test, the max9258 checks receivedprbs data words by comparing them to internally gener- ated prbs data. detected errors are counted in the prbs error register (reg12) in the max9258. whenever the number of detected prbs errors is more than 0, error asserts low. the prbs error register is reset when ecuwrites a 0 to prbsen register (reg4[0]). in this case, error deasserts high immediately if prbs errors were the only reason that error was asserted low. short synchronization pattern the short synchronization pattern is part of the handshak-ing procedure between the max9257 and max9258 after the control channel phase. it is used to resynchronize the max9258? clock and data recovery circuit to the max9257 before the video phase begins. the max9257 transmits the short synchronization pattern when it receives the lock frame from the max9258. the length of short synchronization pattern is dependant on the prate range. when prate is 00 or 01, the short synchroniza- tion pattern consists of 546 words and when prate is 10 or 11, the short synchronization pattern consists of 1090 words. every word is one pixel clock period. long synchronization pattern at power-up or when the max9257 does not receive alock frame from the max9258, the max9257 transmits a long synchronization pattern. the long synchronization pattern consists of 17,410 words. every word is one pixel clock period. when rem is high, if synchroniza- tion is not achieved after 62 attempts, the max9257 resets seren to 0 so that the control channel stays open to allow troubleshooting. when rem is low, the max9257/max9258 continuously tries to reestablish the connection. lock verification (handshaking) at the end of every vertical blanking time, the max9257verifies that the max9258 did not lose lock. the max9258 handshakes with the max9257 to indicate lock status. the handshaking occurs after the channel closes (figures 22 and 23). if the number of decoding errors in a time window did not exceed a certain thresh- old during the last video phase, the max9258 sends back the lock frame that indicates lock. if the max9257 receives the lock frame, the max9257 transmits a short synchronization pattern. the max9258 features a pro- prietary vco mechanism that prevents frequency drift while in the control channel. this allows for successful resynchronization after extended use of control chan- nel. if the number of decoding errors in a time window exceeds a certain threshold, the max9258 loses lock, lock goes low, and the lock frame is not sent. the max9258 also loses lock if handshaking is not suc- cessful. if the max9257 does not receive the lock frame, it transmits a long synchronization pattern before the start of next video phase. when rem = 1, if the lock frame is not received by the max9257 after 62 consec- utive attempts to synchronize, seren is disabled so that the control channel opens permanently for trou- bleshooting. link status (lock and ccen) the lock output indicates whether the max9258 islocked to the max9257. lock is an open-drain output that needs to be pulled up to v cc . lock asserts low to indicate that the max9258 is not locked to themax9257 and high when it is. in the control channel phase, lock stays high if lock is high in the video phase. while in the control channel phase, the max9258 pll frequency is held constant, pclk output is active and data outputs are frozen at their last valid value before entering the control channel. ccen output indicates whether the max9257/max9258 are in the control channel phase or video phase. ccen goes high when the max9257/max9258 are in the control channel phase (table 27). only at initial power-up, ccen goes high before communication in the control channel is ready (see the link power-up section). 32 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel lock ccen indication 1 0 lvds channel active 1 1 control channel active 0 x pll loss of lock table 27. link status downloaded from: http:///
control channel overview of control channel operation the control channel is used by the ecu to programregisters in the max9257, max9258, and peripheral devices (such as a camera) during vertical blanking, after power-up, or when serialization is disabled. control channel communication is half-duplex uart. the peripheral interface on the max9257 can be pro- grammed to be i 2 c or uart. operation of the control channel is synchronized with the vsync input after theecu starts serialization of video data. programmable timers, ecu signal activity, and end frame determine how long the control channel stays open. the control channel remains open as long as there is signal activity from the ecu. when the control channel closes, the lvds serial link is reestablished. once serialization is enabled, the programming of registers (including the control channel overhead time) must be completed within the vertical blanking time to avoid loss of video data. vsync can deassert while control channel remains open after eight pixel clock cycles. the control channel phase begins on the transition of the programmed active edge of vsync_in. in video applications, the vsync signal of the peripheral device is connected to vsync_in on the max9257. in other applications, a different signal can be used to trigger the control channel phase. when the max9257/ max9258 detect the vsync_in transition, the lvds video phase disables and the control channel phase is enabled. the control channel operates in two modes: base and bypass. in base mode, the ecu issues uart com- mands in a specified format to program the max9257/max9258 registers. gpio on the max9257 are also programmed in base mode. uart commands are translated to i 2 c and output to peripheral devices connected to the max9257 when not addressed toeither the max9257 or the max9258. in bypass mode, programming of the max9257/ max9258 registers are temporarily or permanently blocked depending on the programmed value of cto. blocking prevents unintentional programming of the max9257/max9258 registers when the ecu communi- cates with the peripheral using a uart protocol differ- ent than the one specified to program the max9257/ max9258. when the control channel is open, the max9258 continues outputting the pixel clock while hsync and video data are held at the last value. if spread is enabled on the max9258, the pixel clock is spread. control channel overhead control channel overhead consists of lock frame, shortsynchronization sequence, and error frame. the lock frame is transmitted between the max9257 and the max9258 without action by the ecu. the error frame is only sent in response to end frame. when max9257 spread spectrum is enabled, the control channel is entered after spread reaches center frequency. the over- head from vsync falling edge to control channel enable accounts for a maximum of 1400 pixel clock cycles. base mode (details) base mode allows the ecu to communicate with themax9257/max9258 in uart and a peripheral device in i 2 c. uart programming of the peripheral device is not possible in base mode. uart packets from the ecuneed to follow a certain protocol to program the max9257 and the max9258 (figures 28 and 29). packets not addressed to the max9257/max9258 get converted to i 2 c by the max9257 and pass to the peripheral device. the max9257 receives i 2 c packets from the peripheral device and converts them to uart packets to send backto the ecu. to disable communication to the peripheral device, write a 0 to inten (reg8[6] in the max9257 and reg7[6] in the max9258). in base mode, the sto/eto timers and the ef command are used to control the duration of the control channel. sto and eto count up and expire when they reach their programmed value. sto and eto are not enabled at the same time. sto is enabled after ccen goes high. if there is activity from the ecu before sto times out, sto is dis- abled and eto is enabled. the ecu must begin a trans- action within an sto timeout or else the channel closes. the ecu can close the channel by allowing eto to time- out. activity from the ecu resets the eto timer. another way to close the control channel is by sending an end frame (ef). ef closes the channel within 2 to 3 bit times after being received by the max9257/max9258. the default value of ef is 0xff, but can be programmed to any other value besides the max9257 and the max9258 device addresses. the control channel must be closed with ef for control channel errors to be reported. program sto to be longer than the time the ecu takes to respond to opening of channel. program eto to be longer than the time the ecu pauses between transac- tions. as long as the ecu performs transactions, eto is reset and the channel stays open. the ecu must wait 14 or more bit times before address- ing another device during the same control channel ses- sion. failure to wait 14 bit times may result in the packet boundary not being reset. internal handshaking opera- tions are automatically performed after the channel is closed and before the video phase begins. max9257/max9258 ______________________________________________________________________________________ 33 fully programmable serializer/deserializer with uart/i 2 c control channel downloaded from: http:///
max9257/max9258 uart-to-i 2 c converter the uart-to-i 2 c converter accepts uart read or write packets issued by the ecu and converts them to an i 2 c master protocol when in base mode. a slave can use anack or nack to indicate a busy or wait state, but cannot hold scl low to indicate a wait state. multiple slaves are supported. the uart-to-i 2 c conversion delay is less than 22 uart bit times and needs to be taken intoaccount when setting the eto and sto timeout periods for read commands. uart-to-i 2 c converter converts standard uart format to standard i 2 c format (figure 25). this includes data-bit ordering conversion becauseuart transmits the lsb in first while i 2 c transmits the msb first. uart/i 2 c read delay is a maximum 34 bit times when reading from an i 2 c peripheral. the max9257/max9258 store their own 7-bit deviceaddresses in register reg5. all packets not addressed to the max9257/max9258 are forwarded to the uart- to-i 2 c converter. the i 2 c interfaces (sda and scl) are open drain and actively drive a low state. when idle,sda and scl are high impedance and pulled high by a pullup resistor. sda and scl are idle when packets are addressed to the max9257 or max9258. sda and scl are also idle when the i 2 c interface is programmed to be disabled. bypass mode (details) in bypass mode, ecu activity and uart communica-tion from the camera reset the eto and cto timers. this allows the control channel to stay in bypass as long as there is camera activity. in base mode, onlyecu activity resets the eto and cto timers. bypass mode temporarily or permanently blocks pro- gramming of the max9257/max9258. bypass mode allows only uart programming of peripheral device by ecu. there is no i 2 c connection in bypass mode. bypass mode is entered by writing a 0 to intmode and by writ-ing a 1 to inten (table 23). bypass mode disables ecu programming of the max9257/max9258 to allow any uart communication protocol with the peripheral device. once bypass mode is entered, the max9257/max9258 stay in bypass mode until cto times out. in bypass mode, the sto and eto timers determine the control channel duration. cto timer determines whether to revert back to base mode or not, and ef is not recognized. a useful setting in bypass mode is to set sto > cto > eto because this setting is an alternative to permanent bypass (figure 24). use this setting to stay in bypass mode to avoid the overhead of entering from base mode every time the control channel opens. if the ecu uses the channel within a cto timeout, eto is activated and then eto times out before cto. the channel closes because eto times out, but channel stays in bypass mode because cto does not time out. at the next vertical blanking time, bypass mode continues with cto reset and the ecu can immediately send commands to the camera. if the ecu or camera does not use the channel, cto times out before sto. sto closes the channel (because eto is not enabled) if no communication is 34 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel t1 = time to enter control channelt2 = sto timer t3 = cto timer t4 = eto timer t5 = control channel exit time hsk = handshaking between the max9257 & the max9258 = timer reset video video hsk frozen bypass mode base mode video video hsk vsync_in sdi/o ccen t1 t1 t2 t5 t5 t4 t3 t3 t2 tx rx dout_ frozen bypass mode controlchannel sto > cto > eto ecu activity figure 24. cto timing downloaded from: http:///
sent, but since cto timed out, bypass mode ends andbase mode is active for the next vertical blanking period. with sto > cto > eto, bypass mode can be made continuous by having the ecu send real commands or dummy commands (such as a command to a nonexist- ing address) each time the control channel opens. then the ecu does not have to send a command to enter bypass mode each time it wants to program the peripheral device. uart uart frame format the uart frame used to program the max9257 andthe max9258 has a low start bit, eight data bits, an even parity bit and a high stop bit. the data following the start bit is the lsb. with even parity, when there are an odd number of 1s in the data bits (d0 through d7) the parity bit is set to 1. the stop bit is sampled and if it is not high, a frame error is generated (figure 26). uart synchronization frame the synchronization frame must precede any read orwrite packets (figure 26). transitions in the frame cali- brate the oscillators on the max9257/max9258. the baud rate of the synchronization frame sets the operat- ing baud rate of the control channel. at power-up, uart data rate must be between 95kbps to 400kbps. after power-up, uart data rate can be programmed according to tables 28 and 29. data is serialized start- ing with the lsb first. the synchronization frame is 0x54 as shown in figure 27. write packet the ecu writes the sync frame, 7-bit device addressplus read/write bit (r/ w = 0 for write), 8-bit register address, number of bytes to be written, and data bytes(figure 28). the ecu must follow this uart protocol to correctly program the max9257/max9258. max9257/max9258 ______________________________________________________________________________________ 35 fully programmable serializer/deserializer with uart/i 2 c control channel i 2 c reg addr data 0 data n lsb msb lsb msb lsb msb max9257 peripheral ecu max9258 uart msb s slave address i 2 c slave address + wr w a reg address a data 0 a data n a lsb msb lsb msb lsb p figure 25. uart-to-i 2 c conversion start d3 d4 d5 d6 d7 parity stop d0 d1 d2 figure 26. uart frame format 1 0 1 0 1 0 0 0 start synchronization frame stop parity 45 0 1 1 figure 27. uart synchronization frame number of bytes reg address dev addr + r/w sync byte 1 byte n figure 28. uart write packet to max9257/max9258 downloaded from: http:///
max9257/max9258 36 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel read packet the ecu writes the sync frame, 7-bit device addressplus read/write bit (r/ w = 1 for read), 8-bit register address, and number of bytes to be read. theaddressed device responds with read data bytes (figure 29). uart read delay is maximum 4 bit times when reading from the max9257 or the max9258. time between frames up to two high bit times are allowed between frames. reset of packet boundary a high time ranging from 14 uart bit times or moreresets the packet boundary. in this case, the next frame received is assumed to belong to a new packet by the max9257/max9258 and uart-to-i 2 c converter. resetting the boundary is required. not resetting theboundary treats the following packets as part of the first packet, and they may be processed incorrectly. data rate the control channel data rate in base mode is between95kbps to 4.25mbps (table 28). in bypass mode, the allowed data rate is dc to 10mbps (table 29). for data rates faster than 4.25mbps in bypass mode, reg8[5] in max9257 and reg7[5] in max9258 must be set high. set the control channel data rate in base mode by writ- ing to reg8[1:0] in the max9257 and reg7[1:0] in the max9258. these write commands take effect in the next control channel. programming the fast bit takes effect in the same con- trol channel. both the max9257 and the max9258 should have the same settings for fast. it is recom- mended to first program the fast bit in the max9257. programming fast to 1 results in shorter uart pulses on the differential link. max9257/max9258 device address programming the max9257/max9258 have device addresses thatcan be programmed to any 7-bit address. table 30 shows the default addresses. max9257 reg8[1:0]max9258 reg7[1:0] range 00 95kbps?00kbps (default) 01 400kbps?mbps 10 1mbps?.25mbps 11 1mbps?.25mbps table 28. control channel data rate inbase mode max9257 reg8[5]max9258 reg7[5] range 0 dc?.25mbps 1 4.25mbps?0mbps table 29. control channel data rate inbypass mode default device binary hex max9257 1111 1010 0xfa max9258 1111 1000 0xf8 table 30. default device address number of bytes reg address byte 1 byte n dev addr + r/w sync figure 29. uart read packet downloaded from: http:///
max9257/max9258 ______________________________________________________________________________________ 37 fully programmable serializer/deserializer with uart/i 2 c control channel parameter symbol min typ max unit scl clock frequency f scl 11 t uclk* start condition hold time t hd:sta 11 t uclk low period of scl clock t low 0.5 0.5 t uclk high period of scl clock t high 0.5 0.5 t uclk repeated start conditionsetup time t su:sta 0.25 0.25 t uclk data hold time t hd:dat 0.25 0.25 t uclk data setup time t su:dat 0.25 0.25 t uclk setup time for stop condition t su:sto 0.25 0.25 t uclk bus free time t buf 0.5 0.5 t uclk table 31. timing information for i 2 c data rates greater than 400kbps * t uclk is equal to one uart period. i 2 c the max9257 features a uart-to-i 2 c converter that converts uart packets to i 2 c. the uart-to-i 2 c con- verter works as a repeater between the ecu and exter-nal i 2 c slave devices. the max9257 acts as the master and converts uart read/write packets from the ecu toi 2 c read/write for external i 2 c slave devices. for writes, the uart-to-i 2 c converts the uart packets received directly into i 2 c. for reads, the uart-to-i 2 c converter follows the uart packet protocol. the i 2 c scl clock period is approximately the same as the uart bit clockperiod (t uclk ). the i 2 c speed varies with uart speed. i 2 c reads from the peripheral device do not disable the eto timer. choose eto large enough so that i 2 c read commands are not lost due to eto timing out. i 2 c timing the max9257 acts like a master in i 2 c communication with the peripheral device. the max9257 takes lessthan 22 uart bit times to convert uart packets into i 2 c. the scl and sda timings are based on the uart bit clock. the i 2 c data rate is determined by uart and can range from 95kbps to 4.25mbps. the i 2 c timing requirements scale linearly from fast mode to higherspeeds. table 31 shows the i 2 c timing information for data rates greater than 400kbps. the i 2 c parameters scale with t uclk . see figure 30 for timing parameters. applications information prbs test the max9257/max9258 have built-in circuits for testingbit errors on the serial link. the max9257 has a prbs generator and the max9258 has a prbs checker. the length of the prbs pattern is programmable from 2 21 to 2 35 word length or continuous by programming reg9[7:4] in the max9257. in case of errors, errors arecounted in the max9258 prbserr register (reg12), and the error output on the max9258 goes low. to start the test, the ecu writes a 1 to prbsen bit of boththe max9257 and the max9258. the prbs test can be downloaded from: http:///
max9257/max9258 38 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel performed with or without spread spectrum. if the prbstest is programmed to run continuously, the max9257 must be powered down to stop the test. when pro- grammed for a finite number of repetitions, the control channel is enabled after the prbs test finishes and serialization enable (seren) is reset to 0. to start nor- mal operation, the ecu must disable prbsen and enable seren. video data parity parity protection of video data is programmable for par-allel-word widths of 16 bits or less. when programmed, two parity bits are appended to each parallel word latched into the max9257. in the max9258, a 16-bit parity error counter logs parity errors. the error out- put on the max9258 goes low if parity errors exceed aprogrammable threshold. ac-coupling benefits ac-coupling increases the input voltage of the lvdsreceiver to the voltage rating of the capacitor. two capacitors are sufficient for isolation, but four capaci- tors?wo at the serializer output and two at the deseri- alizer input?rovide protection if either end of the cable is shorted to a high voltage. ac-coupling blocks low-frequency ground shifts and common-mode noise. selection of ac-coupling capacitors see figure 31 for calculating the capacitor values forac-coupling depending on the parallel clock frequency. the plot shows minimum capacitor values for two- and four-capacitor-per-link systems. to block the highest common-mode frequency shift, choose the minimum capacitor value shown in figure 31. in general, 0.1?capacitors are sufficient. optimally choosing ac-coupling capacitors voltage droop and the digital sum variaton (dsv) of trans-mitted symbols cause signal transitions to start from dif- ferent voltage levels. because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the lvds receiver termination resistor (r tr ), ac-coupling capacitor value vs. serial-data rate serial-data rate (mbps) capacitor value (nf) 780 720 660 600 540 480 420 20 40 60 0 360 840 four capacitors per link two capacitors per link figure 31. ac-coupling capacitor values vs. clock frequency from 18mhz to 42mhz p t buf t r t hd;sta p s s t hd;sta t low t hd;dat t high t f t su;dat t su;sta t su;sto scl sda figure 30. i 2 c timing parameters downloaded from: http:///
max9257/max9258 ______________________________________________________________________________________ 39 fully programmable serializer/deserializer with uart/i 2 c control channel the lvds driver termination resistor (r td ), and the series ac-coupling capacitors (c). the rc time constant forfour equal-value series capacitors is (c x (r td + r tr ))/4. r td and r tr are required to match the transmission line impedance (usually 100 ). this leaves the capacitor selection to change the system time constant. in the fol-lowing example, the capacitor value for a droop of 2% is calculated: where: c = ac-coupling capacitor (f) t b = bit time(s) dsv = digital sum variation (integer)ln = natural log d = droop (% of signal amplitude) r td = driver termination resistor ( ) r tr = receiver termination resistor ( ) the bit time (t b ) is the serial-clock period or the period of the pixel clock divided by the total number of bits.the maximum dsv for the max9257 encoding equals to the total number of bits transmitted in one pixel clock cycle. this means that t b x dsv t t . the capacitor for 2% maximum droop at 16mhz paral-lel rate clock is: total number of bits is = 10 (data) + 2 (hsync and vsync) + 2 (encoding) + 2 (parity) = 16 c 0.062? jitter due to droop is proportional to the droop and tran-sition time: t j = t tt x d where:t j = jitter(s) t tt = transition time(s) (0 to 100%) d = droop (% of signal amplitude) jitter due to 2% droop and assumed 1ns transition time is:t j = 1ns x 0.02 t j = 20ps the transition time in a real system depends on the fre-quency response of the cable driven by the serializer. the capacitor value decreases for a higher frequency parallel clock and for higher levels of droop and jitter. use high-frequency, surface-mount ceramic capacitors. power-supply circuits and bypassing all single-ended inputs and outputs on the max9257are powered from v ccio . all single-ended outputs on the max9258 are powered from v ccout . v ccio and v ccout can be connected to a +1.71v to +3.6v sup- ply. the input levels or output levels scale with thesesupply rails. board layout separate the lvcmos/lvttl signals and lvds signalsto prevent crosstalk. a four-layer pcb with separate lay- ers for power, ground, lvds, and digital signals is rec- ommended. layout pcb traces for 100 differential characteristic impedance. the trace dimensionsdepend on the type of trace used (microstrip or stripline). note that two 50 pcb traces do not have 100 differential impedance when brought close together?he impedance goes down when the tracesare brought closer. route the pcb traces for an lvds channel (there are two conductors per lvds channel) in parallel to main- tain the differential characteristic impedance. place the 100 (typ) termination resistor at both ends of the lvds driver and receiver. avoid vias. if vias must beused, use only one pair per lvds channel and place the via for each line at the same point along the length of the pcb traces. this way, any reflections occur at the same time. do not make vias into test points for ate. make the pcb traces that make up a differential pair the same length to avoid skew within the differen- tial pair. cables and connectors interconnect for lvds typically has a differential imped-ance of 100 . use cables and connectors that have matched differential impedance to minimize impedancediscontinuities. twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less emi due to magnetic field canceling effects. balanced cables pick up noise as common mode that is rejected by the lvds receiver. c ns = + - - 4 3 91 16 1 02 100 100 . ln( . ) ( ) ? c tdsv dr r b tr td = + - - 4 1 ln( ) ( ) c tdsv dr r b tr td = + 4 1 ln( ) ( ) - downloaded from: http:///
max9257/max9258 40 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel address bits default name description 7:6 10 prate pixel clock frequency range00 = 5mhz to 10mhz 01 = 10mhz to 20mhz 10 = 20mhz to 40mhz (default) 11 = 40mhz to 70mhz 5:4 11 srate serial-data rate range00 = 60mbps to 100mbps 01 = 100mbps to 200mbps 10 = 200mbps to 400mbps 11 = 400mbps to 840mbps (default) 3 0 paren parity enable 0 = disabled (default), 1 = enabled 0 2:0 101 pwidth parallel data width(includes hsync and vsync, excludes dcb, inv, and parity bits) 000 = 10 100 = 18 001 = 12 101 = 18 (default) 010 = 14 110 = 18 011 = 16 111 = 18 7:5 000 spread spread-spectrum settingfor prate ranges 00, 01: all spread options possible for prate ranges 10, 11: maximum spread is 2% 000 = off (default) 100 = off 001 = 1.5% 101 = 3% 010 = 1.75% 110 = 3.5% 011 = 2% 111 = 4% 1 4:0 11111 reserved (set to 11111) control channel start timeout: (sto) times out if ecu does not start using control channel within this amount of timeafter control channel session is enabled. 7:4 1010 stodiv control channel start timeout dividerpixel clock is first divided by: 0000 = 16 1000 = 256 0001 = 16 1001 = 512 0010 = 16 1010 = 1024 (default) 0011 = 16 1011 = 2048 0100 = 16 1100 = 4096 0101 = 32 1101 = 8192 0110 = 64 1110 = 16,384 0111 = 128 1111 = 32,768 2 3:0 0000 stocnt control channel start timeout counterdivided pixel clock is used to count up to (stocnt + 1) max9257 register table choosing i 2 c pullup resistors i 2 c requires pullup resistors to provide a logic-high level to data and clock lines. there are tradeoffs betweenpower dissipation and speed, and a compromise must be made in choosing pullup resistor values. every device connected to the bus introduces some capacitance even when device is not in operation. i 2 c specifies 300ns rise times to go from low to high (30% to 70%) for fast mode,which is defined for a date rate up to 400kbps (see i 2 c specifications for details). to meet the rise time require-ment, choose the pullup resistors so the rise time t r = 0.85r pullup x c bus < 300ns. if the transition time becomes too slow, the setup and hold times may not bemet and waveforms will not be recognized. downloaded from: http:///
max9257/max9258 ______________________________________________________________________________________ 41 fully programmable serializer/deserializer with uart/i 2 c control channel address bits default name description control channel end timeout: (eto) times out if ecu does not use control channel for this amount of time after it hasalready used at least once. 7:4 1010 etodiv control channel end timeout dividerpixel clock is first divided by: 0000 = 16 1000 = 256 0001 = 16 1001 = 512 0010 = 16 1010 = 1024 (default) 0011 = 16 1011 = 2048 0100 = 16 1100 = 4096 0101 = 32 1101 = 8192 0110 = 64 1110 = 16,384 0111 = 128 1111 = 32,768 3 3:0 0000 etocnt control channel end timeout counterdivided pixel clock is used to count up to (etocnt + 1) 7 0 vedge vsync active edge at camera interface0 = falling (default), 1 = rising 6 0 reserved (set to 0) 5 1 ckedge pclk active edge at camera interface0 = falling, 1 = rising (default) 40 p d power mode0 = power-up, 1 = power-down (when rem = 1 default is 1) 3 1 seren serialization enable0 = disabled, 1 = enabled (when rem = 1 default is 0) 2 0 bypfpll bypass filter pll0 = active (default), 1 = bypass 1 0 reserved (set to 0) 4 0 0 prbsen prbs test enable0 = disabled (default), 1 = enabled 7:1 1111101 deviceid 7-bit address of max9257 5 0 0 reserved (set to 0) 7:1 1111111 ef end frame to close control channel 6 0 1 reserved (set to 1) 7:1 1111100 desid 7-bit address id of max9258 7 0 0 reserved (set to 0) max9257 register table (continued) downloaded from: http:///
max9257/max9258 42 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel address bits default name description 7 0 intmode interface mode0 = uart (default), 1 = i 2 c 6 0 inten interface enable0 = disabled (default), 1 = enabled 5 0 fast fast uart transceiver 0 = b i t r ate = d c to 4.25m b p s ( d efaul t) , 1 = b i t r ate = 4.25m b p s to 10m b p s 4:2 000 cto timer to come back from bypass mode (in bit time) 000 = never come back (default) 100 = 64 001 = 16 101 = 80 010 = 32 110 = 96 011 = 48 111 = 112 8 1:0 00 bitrate control channel bit rate range in base mode00 = 95kbps to 400kbps (default) 01 = 400kbps to 1000kbps 10 = 1000kbps to 4250kbps 11 = 1000kbps to 4250kbps 7:4 0000 prbslen prbs test number of words 1111 = continuous else = 2 (prbslen + 21) 3 0 gpio9dir gpio 9 direction 0 = input (default), 1 = output 2 0 gpio8dir gpio 8 direction 0 = input (default), 1 = output 1 0 gpio9* general purpose input output 9 9 0 0 gpio8* general purpose input output 8 7 0 gpio7dir gpio 7 direction 0 = input (default), 1 = output 6 0 gpio6dir gpio 6 direction 0 = input (default), 1 = output 5 0 gpio5dir gpio 5 direction 0 = input (default), 1 = output 4 0 gpio4dir gpio 4 direction 0 = input (default), 1 = output 3 0 gpio3dir gpio 3 direction 0 = input (default), 1 = output 2 0 gpio2dir gpio 2 direction 0 = input (default), 1 = output 1 0 gpio1dir gpio 1 direction 0 = input (default), 1 = output 10 0 0 gpio0dir gpio 0 direction 0 = input (default), 1 = output 7 0 gpio7* general purpose input output 7 6 0 gpio6* general purpose input output 6 5 0 gpio5* general purpose input output 5 4 0 gpio4* general purpose input output 4 3 0 gpio3* general purpose input output 3 2 0 gpio2* general purpose input output 2 1 0 gpio1* general purpose input output 1 11 0 0 gpio0* general purpose input output 0 max9257 register table (continued) downloaded from: http:///
max9257/max9258 ______________________________________________________________________________________ 43 fully programmable serializer/deserializer with uart/i 2 c control channel address bits default name description 7:5 111 preemp lvds driver preemphasis setting 000 = 20% 111 = off (default) 001 = 40% 101 = 20% 010 = 60% 110 = 20% 011 = 80% 100 = 100% 12 4:0 00000 reserved (set to 00000) 7:2 000000 reserved (set to 000000) 13 1:0 00 i 2 cfilt i 2 c glitch filter setting 00 = set according to programmed bit rate (default) 100ns at (95kbps to 400kbps) bit rate 50ns at (400kbps to 1000kbps) bit rate 10ns at (1000kbps to 4250kbps) bit rate 01 = 10ns, 10 = 50ns, 11 = 100ns 7:1 (ro) reserved 14 0 (ro) locked pll locked to pixel clock 15 7:0 (ro) reserved max9257 register table (continued) downloaded from: http:///
max9257/max9258 44 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel address bits default name description 7:6 10 prate pixel clock frequency range00 = 5mhz to 10mhz 01 = 10mhz to 20mhz 10 = 20mhz to 40mhz (default) 11 = 40mhz to 70mhz 5:4 11 srate serial-data rate range00 = 60mbps to 100mbps 01 = 100mbps to 200mbps 10 = 200mbps to 400mbps 11 = 400mbps to 840mbps (default) 3 0 paren parity enable 0 = disabled (default), 1 = enabled 0 2:0 101 pwidth parallel data width(includes hsync and vsync, excludes encoding and parity bits) 000 = 10 100 = 18 001 = 12 101 = 18 (default) 010 = 14 110 = 18 011 = 16 111 = 18 7:6 00 spread spread-spectrum setting 00 = off (default) 10 = off 01 = 2% 11 = 4% 5 0 aer autoerror reset1 = reset error count when control channel ends. 0 = reset upon reading error registers 10, 11, 13 (default) 1 4:0 00000 reserved (set to 000000) control channel start timeout: (sto) times out if ecu does not start using control channel within this amount of timeafter control channel session is enabled. 7:4 1010 stodiv control channel start timeout dividerpixel clock is first divided by : 0000 = 16 1000 = 256 0001 = 16 1001 = 512 0010 = 16 1010 = 1024 (default) 0011 = 16 1011 = 2048 0100 = 16 1100 = 4096 0101 = 32 1101 = 8192 0110 = 64 1110 = 16,384 0111 = 128 1111 = 32,768 2 3:0 0000 stocnt control channel start timeout counterdivided pixel clock is used to count up to (stocnt + 1) max9258 register table downloaded from: http:///
max9257/max9258 ______________________________________________________________________________________ 45 fully programmable serializer/deserializer with uart/i 2 c control channel address bits default name description control channel end timeout: (eto) times out if ecu does not use control channel for this amount of time after it hasalready used at least once. 7:4 1010 etodiv control channel end timeout dividerpixel clock is first divided by: 0000 = 16 1000 = 256 0001 = 16 1001 = 512 0010 = 16 1010 = 1024 (default) 0011 = 16 1011 = 2048 0100 = 16 1100 = 4096 0101 = 32 1101 = 8192 0110 = 64 1110 = 16,384 0111 = 128 1111 = 32,768 3 3:0 0000 etocnt control channel end timeout counterdivided pixel clock is used to count up to (etocnt + 1) 7 0 vedge vsync active edge at ecu interface0 = falling (default), 1 = rising 6 0 hedge hsync active edge at ecu interface0 = falling (default), 1 = rising 51 ckedge pclk active edge at ecu interface0 = falling, 1 = rising (default) 4:1 0000 reserved (set to 0000) 4 0 0 prbsen prbs test enable 0 = disabled (default), 1 = enabled 7:1 1111100 deviceid 7-bit address of max9258 5 0 0 reserved (set to 0) 7:1 1111111 ef end frame to close control channel 6 0 1 reserved (set to 1) 70 intmode interface mode 0 = uart (default), 1 = i 2 c 6 0 inten interface enable 0 = disabled (default), 1 = enabled 5 0 fast fast uart transceiver 0 = bit rate = dc to 4.25mbps (default), 1 = bit rate = 4.25mbps to 10 mbps 4:2 000 cto timer to come back from bypass mode (in bit time) 000 = never come back (default) 100 = 64 001 = 16 101 = 80 010 = 32 110 = 96 011 = 48 111 = 112 7 1:0 00 bitrate control channel bit rate range in base mode00 = 95kbps to 400kbps (default) 01 = 400kbps to 1000kbps 10 = 1000kbps to 4250kbps 11 = 1000kbps to 4250kbps max9258 register table (continued) downloaded from: http:///
max9257/max9258 46 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel address bits default name description 87 : 0 00010000 pathrlo threshold for number of video parity errors (8 lsbs) if the number of errors exceeds this value, err pin is asserted. 97 : 0 00000000 pathrhi threshold for number of video parity errors (8 msbs) if the number of errors exceeds this value, err pin is asserted. 10 7:0 (ro) paerrlo number of video parity errors (8 lsbs) 11 7:0 (ro) paerrhi number of video parity errors (8 msbs) 12 7:0 (ro) prbserr prbs test number of bit errorsautomatically reset when prbs test is disabled 0xff indicates 255 or more errors 7:5 (ro) reserved 4 (ro) desperr parity error during communication with deserializer 3 (ro) desferr frame error during communication with deserializer 2 (ro) serperr parity error during communication with serializer 1 (ro) serferr frame error during communication with serializer 13 0 (ro) i 2 cerr error during communication with camera in i 2 c mode 14 7:0 (ro) reserved max9258 register table (continued) downloaded from: http:///
esd protection the max9257/max9258 esd tolerance is rated forhuman body model, machine model, iec 61000-4-2 and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance for electronic sys- tems. lvds outputs on the max9257 and lvds inputs on the max9258 meet iso 10605 esd protection and iec 61000-4-2 esd protection. all other pins meet the human body model and machine model esd toler-ances. the human body model discharge components are c s = 100pf and r d = 1.5k (figure 33). the iec 61000-4-2 discharge components are c s = 150pf and r d = 330 (figure 32). the iso 10605 discharge com- ponents are c s = 330pf and r d = 2k (figure 34). the machine model discharge components are c s = 200pf and r d = 0 (figure 35). max9257/max9258 ______________________________________________________________________________________ 47 fully programmable serializer/deserializer with uart/i 2 c control channel chip information process: cmos storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1m r d 1.5k c s 100pf figure 33. human body esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2k c s 330pf figure 34. iso 10605 contact discharge esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 0 c s 200pf figure 35. machine model esd test circuit c s 150pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 330 figure 32. iec 61000-4-2 contact discharge esd test circuit downloaded from: http:///
max9257/max9258 48 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel max9257 serializer filter pll bypass blank detect/timer parallel inputs spread pll parallel to serial n x pclk_in 1x vsync polarity encode/ dc balance + fifo lvds tx control tx/rx 1.2v bias sdo- sdo+ uart to i 2 c uart-to-i 2 c bypass osc clk in 1.5% to 4% clk out vsync_in hsync_in sda(rx) scl(tx) din width 100 transmission linez d = 100 din[0:15] pclk_in max9258 deserializer spread pll 2% or 4% blank detect/timer pll serial to parallel 1x vsync polarity decode/ dc balance + fifo lvds rx control tx/rx 1.2v bias sdi+ sdi- uart osc freq detect clk out clk in vsync_out hsync_out rx tx dout width 100 dout[0:15] pclk_out n x pclk_in parallel outputs address functional diagram downloaded from: http:///
max9257/max9258 ______________________________________________________________________________________ 49 fully programmable serializer/deserializer with uart/i 2 c control channel max9257 tqfn-ep connect ep to gnd top view 35 36 34 33 12 11 13 gnd din10/gpio2din11/gpio2 din12/gpio3 din13/gpio5 14 vccio sdo+gnd lvds gnd spll v cclvds rem din0v ccspll gpio9 12 gnd 45 6 7 27 28 29 3026 24 23 22 din3 din4 v ccio sda/rx scl/tx pclk_in din9/gpio1 sdo- 3 25 37 din5 vsync_in 38 39 40 din6 din7 din8/gpio0 hsync_in din15/gpio7 gnd v cc 32 15 gnd din2 31 16 17 18 19 20 v cc din14/gpio6 gnd fpll v ccfpll gpio8 89 10 21 din1 + pin configurations n.c.din0 rem v cclvds sdo+sdo- gnd lvds gnd spll v ccspll gpio9gpio8 n.c. n.c. v ccio gnd din9/gpio1 din10/gpio2din11/gpio3 din12/gpio4 din13/gpio5 din14/gpio6 gnd fpll v ccfpll n.c. 12 3 4 5 6 7 8 9 1011 12 3635 34 33 32 31 30 29 28 27 26 25 lqfp max9257 n.c. gnd din15/gpio7 hsync_in vsync_in pclk_in scl/tx sda/rx 1314 15 16 17 18 19 20 21 22 23 24 4847 46 45 44 43 42 41 40 39 38 37 n.c.din8/gpio0 din7 din6 din5 din4 din3 gnd v cc din2din1 n.c. v ccio gnd v cc n.c. + n.c.dout7 dout8 dout9 dout10 dout11 dout12 dout13 dout14 gnd spll v ccspll n.c. n.c. v cc gnd pd v cclvds sdi- sdi+ gnd lvds gnd pll v ccpll error n.c. 12 3 4 5 6 7 8 9 1011 12 3635 34 33 32 31 30 29 28 27 26 25 lqfp max9258 n.c. gnd rx tx lock pclk_out vsync_out 1314 15 16 17 18 19 20 21 22 23 24 4847 46 45 44 43 42 41 40 39 38 37 gnd out ccendout0 dout1 dout2 dout3 dout4 dout5 dout6 v ccout gnd out n.c. dout15 v ccout gnd out n.c. hsync_out + downloaded from: http:///
max9257/max9258 50 ______________________________________________________________________________________ fully programmable serializer/deserializer with uart/i 2 c control channel max9258 ecu c cmos image sensor serial i/o max9257 serial i/o data 10 control unit 100 100 remote camera assembly pclk hsync vsync lock tx rx controlchannel data 10 pclk hsync vsync serialized digital video up to 20m cable length scl sda typical operating circuit downloaded from: http:///
max9257/max9258 ______________________________________________________________________________________ 51 fully programmable serializer/deserializer with uart/i 2 c control channel package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . package type package code document no. 40 tqfn t4055+1 21-0140 48 lqfp c48+3 21-0054 downloaded from: http:///
max9257/max9258 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 52 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. fully programmable serializer/deserializer with uart/i 2 c control channel revision history revision number revision date description pages changed 0 6/08 initial release 1 3/09 added automotive qualified part numbers to ordering information .1 downloaded from: http:///

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